Heinz Honigschmid

Person

Essex Jct, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Random access semiconductor memory with reduced signal overcoupling
- Patent number 6,826,075
- Issue date Nov 30, 2004
- Infineon Technologies AG
- Dietmar Gogl
- G11 - INFORMATION STORAGE
Information Patent Grant
Magnetic memory configuration
- Patent number 6,816,406
- Issue date Nov 9, 2004
- Infineon Technologies AG
- Heinz Hönigschmid
- G11 - INFORMATION STORAGE
Information Patent Grant
MRAM configuration having selection transistors with a large channe...
- Patent number 6,803,618
- Issue date Oct 12, 2004
- Infineon Technologies AG
- Heinz Hönigschmid
- G11 - INFORMATION STORAGE
Information Patent Grant
Data memory with a plurality of memory banks
- Patent number 6,741,513
- Issue date May 25, 2004
- Infineon Technologies AG
- Heinz Hönigschmid
- G11 - INFORMATION STORAGE
Information Patent Grant
Ferroelectric memory configuration and a method for producing the c...
- Patent number 6,664,158
- Issue date Dec 16, 2003
- Infineon Technologies AG
- Christine Dehm
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated memory with memory cell array
- Patent number 6,657,916
- Issue date Dec 2, 2003
- Infineon Technologies AG
- Heinz Hönigschmid
- G11 - INFORMATION STORAGE
Information Patent Grant
Process for producing a capacitor configuration
- Patent number 6,645,809
- Issue date Nov 11, 2003
- Infineon Technologies AG
- Heinz Hönigschmid
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit configuration for controlling write and read operations in...
- Patent number 6,577,528
- Issue date Jun 10, 2003
- Infineon Technologies AG
- Dietmar Gogl
- G11 - INFORMATION STORAGE
Information Patent Grant
Fuse circuit configuration
- Patent number 6,545,526
- Issue date Apr 8, 2003
- Infineon Technologies AG
- Heinz Hönigschmid
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory and corresponding operating method
- Patent number 6,538,950
- Issue date Mar 25, 2003
- Infineon Technologies AG
- Thomas Böhm
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for operating a ferroelectric memory configuration and a fer...
- Patent number 6,538,913
- Issue date Mar 25, 2003
- Infineon Technologies AG
- Heinz Hönigschmid
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory with redundancy
- Patent number 6,525,974
- Issue date Feb 25, 2003
- Infineon Technologies AG
- Ernst Neuhold
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated semiconductor memory having memory cells with a ferroele...
- Patent number 6,515,890
- Issue date Feb 4, 2003
- Infineon Technologies AG
- Robert Esterl
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit configuration and method for accelerating aging in an MRAM
- Patent number 6,507,512
- Issue date Jan 14, 2003
- Infineon Technologies AG
- Heinz Hönigschmid
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory having memory cells and reference cells, and oper...
- Patent number 6,487,128
- Issue date Nov 26, 2002
- Infineon Technologies AG
- Thomas Böhm
- G11 - INFORMATION STORAGE
Information Patent Grant
Decoder element for generating an output signal having three differ...
- Patent number 6,480,055
- Issue date Nov 12, 2002
- Infineon Technologies AG
- Thomas Böhm
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor circuit configuration
- Patent number 6,480,044
- Issue date Nov 12, 2002
- Infineon Technologies AG
- Georg Braun
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory having memory cells that each include a ferroelec...
- Patent number 6,477,078
- Issue date Nov 5, 2002
- Infineon Technologies AG
- Heinz Hönigschmid
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory having memory cells and reference cells, and corr...
- Patent number 6,459,626
- Issue date Oct 1, 2002
- Infineon Technologies AG
- Thomas Böhm
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory configuration with a refresh logic circuit, an...
- Patent number 6,452,852
- Issue date Sep 17, 2002
- Infineon Technologies AG
- Thomas Böhm
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for operating an integrated memory
- Patent number 6,445,607
- Issue date Sep 3, 2002
- Infineon Technologies AG
- Robert Esterl
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory
- Patent number 6,442,100
- Issue date Aug 27, 2002
- Infineon Technologies AG
- Thomas Böhm
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit configuration for reading a memory cell having a ferroelect...
- Patent number 6,434,039
- Issue date Aug 13, 2002
- Infineon Technologies AG
- Georg Braun
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated ferroelectric memory having plate lines selected by a co...
- Patent number 6,430,080
- Issue date Aug 6, 2002
- Infineon Technologies AG
- Heinz Hönigschmid
- G11 - INFORMATION STORAGE
Information Patent Grant
Ferroelectric memory array composed of a multiplicity of memory cel...
- Patent number 6,424,558
- Issue date Jul 23, 2002
- Infineon Technologies AG
- Georg Braun
- G11 - INFORMATION STORAGE
Information Patent Grant
MRAM memory cell
- Patent number 6,424,563
- Issue date Jul 23, 2002
- Infineon Technologies AG
- Heinz Hönigschmid
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Integrated memory with redundancy and method for repairing an integ...
- Patent number 6,396,750
- Issue date May 28, 2002
- Infineon Technologies AG
- Heinz Hönigschmid
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit configuration for generating a reference voltage for readin...
- Patent number 6,392,918
- Issue date May 21, 2002
- Infineon Technologies AG
- Georg Braun
- G11 - INFORMATION STORAGE
Information Patent Grant
Decoder element for producing an output signal having three differe...
- Patent number 6,392,445
- Issue date May 21, 2002
- Infineon Technologies AG
- Thomas Röhr
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated semiconductor memory with redundant units for memory cells
- Patent number 6,353,562
- Issue date Mar 5, 2002
- Infineon Technologies AG
- Thomas Böhm
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Magnetic memory configuration
- Publication number 20040100836
- Publication date May 27, 2004
- Heinz Honigschmid
- G11 - INFORMATION STORAGE
Information Patent Application
MRAM configuration having selection transistors with a large channe...
- Publication number 20030218926
- Publication date Nov 27, 2003
- Heinz Honigschmid
- G11 - INFORMATION STORAGE
Information Patent Application
Ferroelectric memory configuration and a method for producing the c...
- Publication number 20020123203
- Publication date Sep 5, 2002
- Christine Dehm
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated memory
- Publication number 20020116591
- Publication date Aug 22, 2002
- Heinz Honigschmid
- G11 - INFORMATION STORAGE
Information Patent Application
Data memory with a plurality of memory banks
- Publication number 20020114206
- Publication date Aug 22, 2002
- Heinz Honigschmid
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit configuration for controlling write and read operations in...
- Publication number 20020080661
- Publication date Jun 27, 2002
- Dietmar Gogl
- G11 - INFORMATION STORAGE
Information Patent Application
Process for producing a capacitor configuration
- Publication number 20020081790
- Publication date Jun 27, 2002
- Heinz Honigschmid
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated memory having memory cells and reference cells, and corr...
- Publication number 20020071317
- Publication date Jun 13, 2002
- Thomas Bohm
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED FERROELECTRIC MEMORY HAVING PLATE LINES SELECTED BY A CO...
- Publication number 20020054501
- Publication date May 9, 2002
- Heinz Honigschmid
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit configuration and method for accelerating aging in an MRAM
- Publication number 20020050840
- Publication date May 2, 2002
- Heinz Honigschmid
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated memory having memory cells that each include a ferroelec...
- Publication number 20020044478
- Publication date Apr 18, 2002
- Heinz Honigschmid
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated memory and corresponding operating method
- Publication number 20020044493
- Publication date Apr 18, 2002
- Thomas Bohm
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated memory having memory cells and reference cells, and oper...
- Publication number 20020027816
- Publication date Mar 7, 2002
- Thomas Bohm
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit configuration for reading a memory cell having a ferroelect...
- Publication number 20020024836
- Publication date Feb 28, 2002
- Georg Braun
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated memory with redundancy
- Publication number 20020015337
- Publication date Feb 7, 2002
- Ernst Neuhold
- G11 - INFORMATION STORAGE
Information Patent Application
Random access semiconductor memory with reduced signal overcoupling
- Publication number 20020012266
- Publication date Jan 31, 2002
- Dietmar Gogl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MRAM memory cell
- Publication number 20020008989
- Publication date Jan 24, 2002
- Heinz Honigschmid
- B82 - NANO-TECHNOLOGY
Information Patent Application
Decoder element for generating an output signal having three differ...
- Publication number 20020008564
- Publication date Jan 24, 2002
- Thomas Bohm
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated memory with redundancy and method for repairing an integ...
- Publication number 20020003728
- Publication date Jan 10, 2002
- Heinz Honigschmid
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated memory
- Publication number 20020003735
- Publication date Jan 10, 2002
- Thomas Bohm
- G11 - INFORMATION STORAGE
Information Patent Application
Fuse circuit configuration
- Publication number 20010054948
- Publication date Dec 27, 2001
- Heinz Honigschmid
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated semiconductor memory having memory cells with a ferroele...
- Publication number 20010038561
- Publication date Nov 8, 2001
- Robert Esterl
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit configuration for generating a reference voltage for readin...
- Publication number 20010038557
- Publication date Nov 8, 2001
- Georg Braun
- G11 - INFORMATION STORAGE
Information Patent Application
Method for operating a ferroelectric memory configuration and a fer...
- Publication number 20010036099
- Publication date Nov 1, 2001
- Heinz Honigschmid
- G11 - INFORMATION STORAGE
Information Patent Application
Method for operating an integrated memory
- Publication number 20010036100
- Publication date Nov 1, 2001
- Robert Esterl
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor circuit configuration
- Publication number 20010028090
- Publication date Oct 11, 2001
- Georg Braun
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor memory configuration with a refresh logic circuit, an...
- Publication number 20010026491
- Publication date Oct 4, 2001
- Thomas Bohm
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated semiconductor memory with redundant units for memory cells
- Publication number 20010021134
- Publication date Sep 13, 2001
- Thomas Bohm
- G11 - INFORMATION STORAGE
Information Patent Application
Ferroelectric memory array
- Publication number 20010012213
- Publication date Aug 9, 2001
- Georg Braun
- H01 - BASIC ELECTRIC ELEMENTS

Heinz Honigschmid

Person

Patents Grantslast 30 patents

Random access semiconductor memory with reduced signal overcoupling

Magnetic memory configuration

MRAM configuration having selection transistors with a large channe...

Data memory with a plurality of memory banks

Ferroelectric memory configuration and a method for producing the c...

Integrated memory with memory cell array

Process for producing a capacitor configuration

Circuit configuration for controlling write and read operations in...

Fuse circuit configuration

Integrated memory and corresponding operating method

Method for operating a ferroelectric memory configuration and a fer...

Integrated memory with redundancy

Integrated semiconductor memory having memory cells with a ferroele...

Circuit configuration and method for accelerating aging in an MRAM

Integrated memory having memory cells and reference cells, and oper...

Decoder element for generating an output signal having three differ...

Semiconductor circuit configuration

Integrated memory having memory cells that each include a ferroelec...

Integrated memory having memory cells and reference cells, and corr...

Semiconductor memory configuration with a refresh logic circuit, an...

Method for operating an integrated memory

Integrated memory

Circuit configuration for reading a memory cell having a ferroelect...

Integrated ferroelectric memory having plate lines selected by a co...

Ferroelectric memory array composed of a multiplicity of memory cel...

MRAM memory cell

Integrated memory with redundancy and method for repairing an integ...

Circuit configuration for generating a reference voltage for readin...

Decoder element for producing an output signal having three differe...

Integrated semiconductor memory with redundant units for memory cells

Patents Applicationslast 30 patents

Magnetic memory configuration

MRAM configuration having selection transistors with a large channe...

Ferroelectric memory configuration and a method for producing the c...

Integrated memory

Data memory with a plurality of memory banks

Circuit configuration for controlling write and read operations in...

Process for producing a capacitor configuration

Integrated memory having memory cells and reference cells, and corr...

INTEGRATED FERROELECTRIC MEMORY HAVING PLATE LINES SELECTED BY A CO...

Circuit configuration and method for accelerating aging in an MRAM

Integrated memory having memory cells that each include a ferroelec...

Integrated memory and corresponding operating method

Integrated memory having memory cells and reference cells, and oper...

Circuit configuration for reading a memory cell having a ferroelect...

Integrated memory with redundancy

Random access semiconductor memory with reduced signal overcoupling

MRAM memory cell

Decoder element for generating an output signal having three differ...

Integrated memory with redundancy and method for repairing an integ...

Integrated memory

Fuse circuit configuration

Integrated semiconductor memory having memory cells with a ferroele...

Circuit configuration for generating a reference voltage for readin...

Method for operating a ferroelectric memory configuration and a fer...

Method for operating an integrated memory

Semiconductor circuit configuration

Semiconductor memory configuration with a refresh logic circuit, an...

Integrated semiconductor memory with redundant units for memory cells

Ferroelectric memory array