Hing Wong

Person

Jericho, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Structure and method of a column redundancy memory
- Patent number 6,327,197
- Issue date Dec 4, 2001
- Silicon Access Networks, Inc.
- Juhan Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Structure and method of an encoded ternary content addressable memo...
- Patent number 6,288,922
- Issue date Sep 11, 2001
- Silicon Access Networks, Inc.
- Hing Wong
- G11 - INFORMATION STORAGE
Information Patent Grant
Parallel test circuit and method for wide input/output DRAM
- Patent number 6,262,928
- Issue date Jul 17, 2001
- Silicon Access Networks, Inc.
- Juhan Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
High performance CMOS word-line driver
- Patent number 6,236,617
- Issue date May 22, 2001
- International Business Machines Corporation
- Louis L. Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Fabrication of interconnects with two different thicknesses
- Patent number 6,136,686
- Issue date Oct 24, 2000
- International Business Machines Corporation
- Jeffrey P. Gambino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Column redundancy based on column slices
- Patent number 6,115,300
- Issue date Sep 5, 2000
- Silicon Access Technology, Inc.
- Ali Massoumi
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory having hierarchical bit line and/or word line...
- Patent number 6,069,815
- Issue date May 30, 2000
- Siemens Aktiengesellschaft
- Gerhard Mueller
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for redundancy word line replacement in a repa...
- Patent number 5,963,489
- Issue date Oct 5, 1999
- International Business Machines Corporation
- Toshiaki Kirihata
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method to externally adjust internal circuit timing
- Patent number 5,903,512
- Issue date May 11, 1999
- Siemens Aktiengesellschaft
- Hing Wong
- G11 - INFORMATION STORAGE
Information Patent Grant
Floating bitline test mode with digitally controllable bitline equa...
- Patent number 5,848,008
- Issue date Dec 8, 1998
- Siemens Aktiengesellschaft
- Toshiaki Kirihata
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked electrical device having regions of electrical isolation an...
- Patent number 5,804,853
- Issue date Sep 8, 1998
- International Business Machines Corporation
- John Edward Cronin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit and method to externally adjust internal circuit timing
- Patent number 5,745,430
- Issue date Apr 28, 1998
- Siemens Aktiengesellschaft
- Hing Wong
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of making corner protected shallow trench field effect trans...
- Patent number 5,741,738
- Issue date Apr 21, 1998
- International Business Machines Corporation
- Jack A. Mandelman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Row redundancy block architecture
- Patent number 5,691,946
- Issue date Nov 25, 1997
- International Business Machines Corporation
- John DeBrosse
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of testing a random access memory
- Patent number 5,619,460
- Issue date Apr 8, 1997
- International Business Machines Corporation
- Toshiaki Kirihata
- G11 - INFORMATION STORAGE
Information Patent Grant
Latched row decoder for a random access memory
- Patent number 5,615,164
- Issue date Mar 25, 1997
- International Business Machines Corporation
- Toshiaki Kirihata
- G11 - INFORMATION STORAGE
Information Patent Grant
DRAM signal margin test method
- Patent number 5,610,867
- Issue date Mar 11, 1997
- International Business Machines Corporation
- John K. DeBrosse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of making stacked electrical device having regions of electr...
- Patent number 5,602,051
- Issue date Feb 11, 1997
- International Business Machines Corporation
- John E. Cronin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dynamic random access memory with a simple test arrangement
- Patent number 5,559,739
- Issue date Sep 24, 1996
- International Business Machines Corporation
- John K. DeBrosse
- G11 - INFORMATION STORAGE
Information Patent Grant
P-MOSFETS with enhanced anomalous narrow channel effect
- Patent number 5,559,050
- Issue date Sep 24, 1996
- International Business Machines Corporation
- Johann Alsmeier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making corrugated vertical stack capacitor (CVSTC)
- Patent number 5,556,802
- Issue date Sep 17, 1996
- International Business Machines Corporation
- Paul E. Bakeman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Corner protected shallow trench isolation device
- Patent number 5,521,422
- Issue date May 28, 1996
- International Business Machines Corporation
- Jack A. Mandelman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Random access memory and an improved bus arrangement therefor
- Patent number 5,517,442
- Issue date May 14, 1996
- International Business Machines Corporation
- Toshiaki Kirihata
- G11 - INFORMATION STORAGE
Information Patent Grant
Hybrid open folded sense amplifier architecture for a memory device
- Patent number 5,276,641
- Issue date Jan 4, 1994
- International Business Machines Corporation
- Edmund J. Sprogis
- G11 - INFORMATION STORAGE

Person

Patents Grantslast 30 patents

Structure and method of a column redundancy memory

Structure and method of an encoded ternary content addressable memo...

Parallel test circuit and method for wide input/output DRAM

High performance CMOS word-line driver

Fabrication of interconnects with two different thicknesses

Column redundancy based on column slices

Semiconductor memory having hierarchical bit line and/or word line...

Method and apparatus for redundancy word line replacement in a repa...

Circuit and method to externally adjust internal circuit timing

Floating bitline test mode with digitally controllable bitline equa...

Stacked electrical device having regions of electrical isolation an...

Circuit and method to externally adjust internal circuit timing

Method of making corner protected shallow trench field effect trans...

Row redundancy block architecture

Method of testing a random access memory

Latched row decoder for a random access memory

DRAM signal margin test method

Method of making stacked electrical device having regions of electr...

Dynamic random access memory with a simple test arrangement

P-MOSFETS with enhanced anomalous narrow channel effect

Method of making corrugated vertical stack capacitor (CVSTC)

Corner protected shallow trench isolation device

Random access memory and an improved bus arrangement therefor

Hybrid open folded sense amplifier architecture for a memory device