Hongxia FENG

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Selectively roughened copper architectures for low insertion loss c...
- Patent number 12,033,930
- Issue date Jul 9, 2024
- Intel Corporation
- Jieying Kong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Architecture to manage FLI bump height delta and reliability needs...
- Patent number 11,955,448
- Issue date Apr 9, 2024
- Intel Corporation
- Jung Kyu Han
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Etch barrier for microelectronic packaging conductive structures
- Patent number 11,948,898
- Issue date Apr 2, 2024
- Intel Corporation
- Kristof Darmawikarta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Patternable die attach materials and processes for patterning
- Patent number 11,923,312
- Issue date Mar 5, 2024
- Intel Corporation
- Bai Nie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to enable 30 microns pitch EMIB or below
- Patent number 11,676,891
- Issue date Jun 13, 2023
- Intel Corporation
- Hongxia Feng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lithographically defined vertical interconnect access (VIA) in diel...
- Patent number 11,640,934
- Issue date May 2, 2023
- Intel Corporation
- Meizi Jiao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to enable 30 microns pitch EMIB or below
- Patent number 11,088,062
- Issue date Aug 10, 2021
- Intel Corporation
- Hongxia Feng
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
2D FILLERS FOR REDUCED CTE FOR PID
- Publication number 20240332125
- Publication date Oct 3, 2024
- Intel Corporation
- Kyle ARRINGTON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS, SYSTEMS, APPARATUS, AND ARTICLES OF MANUFACTURE TO IMPROVE...
- Publication number 20240312865
- Publication date Sep 19, 2024
- Intel Corporation
- Kyle Arrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND APPARATUS TO REDUCE VARIATION IN HEIGHT OF BUMPS AFTER...
- Publication number 20240243087
- Publication date Jul 18, 2024
- Intel Corporation
- Ryan Joseph Carrazzone
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OPTICAL SEMICONDUCTOR PACKAGE AND METHOD
- Publication number 20240219655
- Publication date Jul 4, 2024
- Intel Corporation
- Haobo Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OPTICAL SEMICONDUCTOR PACKAGE AND METHOD
- Publication number 20240219660
- Publication date Jul 4, 2024
- Intel Corporation
- Bohan Shan
- G02 - OPTICS
Information Patent Application
DIE ATTACH IN GLASS CORE PACKAGE THROUGH ORGANIC-TO-ORGANIC BONDING
- Publication number 20240222345
- Publication date Jul 4, 2024
- Intel Corporation
- Bohan Shan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS AND METHOD FOR ATTACHING AN OPTICAL COMPONENT USING HYBRI...
- Publication number 20240222243
- Publication date Jul 4, 2024
- Intel Corporation
- Bohan Shan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS, SYSTEMS, APPARATUS, AND ARTICLES OF MANUFACTURE TO PRODUCE...
- Publication number 20240222259
- Publication date Jul 4, 2024
- Intel Corporation
- Haobo Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENABLING COPPER RECESS FLATTENING THROUGH BLOCKED COPPER ETCHING PR...
- Publication number 20240222130
- Publication date Jul 4, 2024
- Intel Corporation
- Shaojiang CHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND APPARATUS FOR OPTICAL THERMAL TREATMENT IN SEMICONDUCTO...
- Publication number 20240222301
- Publication date Jul 4, 2024
- Intel Corporation
- Bohan Shan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND APPARATUS TO REDUCE SOLDER BUMP BRIDGING BETWEEN TWO SU...
- Publication number 20240222304
- Publication date Jul 4, 2024
- Intel Corporation
- Bohan Shan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRICAL LAYER WITH ROUGHENED SURFACES
- Publication number 20240222136
- Publication date Jul 4, 2024
- Intel Corporation
- Bohan Shan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GLASS SUBSTRATE DEVICE WITH PLATED THROUGH HOLES
- Publication number 20240222257
- Publication date Jul 4, 2024
- Intel Corporation
- Bohan Shan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND APPARATUS TO PREVENT OVER-ETCH IN SEMICONDUCTOR PACKAGES
- Publication number 20240222283
- Publication date Jul 4, 2024
- Intel Corporation
- Hongxia Feng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GLASS SUBSTRATE FABRICATION USING HYBRID BONDING
- Publication number 20240222210
- Publication date Jul 4, 2024
- Intel Corporation
- Bohan Shan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS AND METHOD FOR ATTACHING AN OPTICAL COMPONENT USING NO RE...
- Publication number 20240222238
- Publication date Jul 4, 2024
- Intel Corporation
- Bohan Shan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GLASS SUBSTRATE DEVICE WITH EMBEDDED COMPONENTS
- Publication number 20240213170
- Publication date Jun 27, 2024
- Intel Corporation
- Bohan Shan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS, SYSTEMS, APPARATUS, AND ARTICLES OF MANUFACTURE TO COOL IN...
- Publication number 20240213116
- Publication date Jun 27, 2024
- Intel Corporation
- Kyle Arrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GLASS SUBSTRATE DEVICE WITH THROUGH GLASS CAVITY
- Publication number 20240215269
- Publication date Jun 27, 2024
- Intel Corporation
- Bohan Shan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW DIE HEIGHT GLASS SUBSTRATE DEVICE AND METHOD
- Publication number 20240213169
- Publication date Jun 27, 2024
- Intel Corporation
- Bohan Shan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GLASS LAYER WITH LITHO DEFINED THROUGH-GLASS VIA
- Publication number 20240203806
- Publication date Jun 20, 2024
- Intel Corporation
- Bohan Shan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DRY FILM PHOTORESIST WET LAMINATION AND METHOD
- Publication number 20240203853
- Publication date Jun 20, 2024
- Intel Corporation
- Bohan Shan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE ARCHITECTURES WITH CORE AND/OR BUILD-UP...
- Publication number 20240186228
- Publication date Jun 6, 2024
- Intel Corporation
- Haobo Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE ARCHITECTURES WITH CORE AND/OR BUILD-UP...
- Publication number 20240186227
- Publication date Jun 6, 2024
- Intel Corporation
- Haobo Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SINGULATION OF INTEGRATED CIRCUIT PACKAGE SUBSTRATES WITH GLASS CORES
- Publication number 20240112971
- Publication date Apr 4, 2024
- Intel Corporation
- Yiqun Bai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PATTERNABLE DIE ATTACH MATERIALS AND PROCESSES FOR PATTERNING
- Publication number 20240088052
- Publication date Mar 14, 2024
- Intel Corporation
- Bai NIE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THROUGH GLASS VIAS (TGVS) IN GLASS CORE SUBSTRATES
- Publication number 20240071848
- Publication date Feb 29, 2024
- Intel Corporation
- Bohan SHAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID BONDING A DIE TO A SUBSTRATE WITH VIAS CONNECTING METAL PADS...
- Publication number 20230317653
- Publication date Oct 5, 2023
- Intel Corporation
- Hongxia FENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL PCB FOR TOPSIDE POWER DELIVERY
- Publication number 20230317706
- Publication date Oct 5, 2023
- Intel Corporation
- Kyle ARRINGTON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRICAL TRACES ON GLASS CORES IN INTEGRATED CIRCUIT PACKAGES AND...
- Publication number 20230197540
- Publication date Jun 22, 2023
- Intel Corporation
- Kristof Darmawikarta
- H01 - BASIC ELECTRIC ELEMENTS

Hongxia FENG

Person

Patents Grantslast 30 patents

Selectively roughened copper architectures for low insertion loss c...

Architecture to manage FLI bump height delta and reliability needs...

Etch barrier for microelectronic packaging conductive structures

Patternable die attach materials and processes for patterning

Method to enable 30 microns pitch EMIB or below

Lithographically defined vertical interconnect access (VIA) in diel...

Method to enable 30 microns pitch EMIB or below

Patents Applicationslast 30 patents

2D FILLERS FOR REDUCED CTE FOR PID

METHODS, SYSTEMS, APPARATUS, AND ARTICLES OF MANUFACTURE TO IMPROVE...

METHODS AND APPARATUS TO REDUCE VARIATION IN HEIGHT OF BUMPS AFTER...

OPTICAL SEMICONDUCTOR PACKAGE AND METHOD

OPTICAL SEMICONDUCTOR PACKAGE AND METHOD

DIE ATTACH IN GLASS CORE PACKAGE THROUGH ORGANIC-TO-ORGANIC BONDING

APPARATUS AND METHOD FOR ATTACHING AN OPTICAL COMPONENT USING HYBRI...

METHODS, SYSTEMS, APPARATUS, AND ARTICLES OF MANUFACTURE TO PRODUCE...

ENABLING COPPER RECESS FLATTENING THROUGH BLOCKED COPPER ETCHING PR...

METHODS AND APPARATUS FOR OPTICAL THERMAL TREATMENT IN SEMICONDUCTO...

METHODS AND APPARATUS TO REDUCE SOLDER BUMP BRIDGING BETWEEN TWO SU...

ELECTRICAL LAYER WITH ROUGHENED SURFACES

GLASS SUBSTRATE DEVICE WITH PLATED THROUGH HOLES

METHODS AND APPARATUS TO PREVENT OVER-ETCH IN SEMICONDUCTOR PACKAGES

GLASS SUBSTRATE FABRICATION USING HYBRID BONDING

APPARATUS AND METHOD FOR ATTACHING AN OPTICAL COMPONENT USING NO RE...

GLASS SUBSTRATE DEVICE WITH EMBEDDED COMPONENTS

METHODS, SYSTEMS, APPARATUS, AND ARTICLES OF MANUFACTURE TO COOL IN...

GLASS SUBSTRATE DEVICE WITH THROUGH GLASS CAVITY

LOW DIE HEIGHT GLASS SUBSTRATE DEVICE AND METHOD

GLASS LAYER WITH LITHO DEFINED THROUGH-GLASS VIA

DRY FILM PHOTORESIST WET LAMINATION AND METHOD

INTEGRATED CIRCUIT PACKAGE ARCHITECTURES WITH CORE AND/OR BUILD-UP...

INTEGRATED CIRCUIT PACKAGE ARCHITECTURES WITH CORE AND/OR BUILD-UP...

SINGULATION OF INTEGRATED CIRCUIT PACKAGE SUBSTRATES WITH GLASS CORES

PATTERNABLE DIE ATTACH MATERIALS AND PROCESSES FOR PATTERNING

THROUGH GLASS VIAS (TGVS) IN GLASS CORE SUBSTRATES

HYBRID BONDING A DIE TO A SUBSTRATE WITH VIAS CONNECTING METAL PADS...

METAL PCB FOR TOPSIDE POWER DELIVERY

ELECTRICAL TRACES ON GLASS CORES IN INTEGRATED CIRCUIT PACKAGES AND...