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Jacob Avidan
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Los Altos, CA, US
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Patents Grants
last 30 patents
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Patent Grant
Method for repeated block modification for chip routing
Patent number
8,893,070
Issue date
Nov 18, 2014
Synopsys, Inc.
Jacob Avidan
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Method for repeated block modification for chip routing
Patent number
8,407,650
Issue date
Mar 26, 2013
Synopsis, Inc.
Jacob Avidan
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Method for repeated block timing analysis
Patent number
7,971,168
Issue date
Jun 28, 2011
Magna Design Automation, Inc.
Robert Swanson
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Standard block architecture for integrated circuit design
Patent number
6,536,028
Issue date
Mar 18, 2003
Ammocore Technologies, Inc.
Athanassios Katsioulas
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Integrated circuit architecture with standard blocks
Patent number
6,467,074
Issue date
Oct 15, 2002
Ammocore Technology, Inc.
Athanassios Katsioulas
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Circuit analyzer of black, gray and transparent elements
Patent number
6,158,022
Issue date
Dec 5, 2000
Synopsys, Inc.
Jacob Avidan
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Circuit analyzer of black, gray and transparent elements
Patent number
5,740,347
Issue date
Apr 14, 1998
Synopsys, Inc.
Jacob Avidan
G06 - COMPUTING CALCULATING COUNTING
Patents Applications
last 30 patents
Information
Patent Application
METHOD FOR REPEATED BLOCK MODIFICATION FOR CHIP ROUTING
Publication number
20130227511
Publication date
Aug 29, 2013
Synopsys, Inc.
Jacob Avidan
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Placement-Driven Physical-Hierarchy Generation
Publication number
20070245281
Publication date
Oct 18, 2007
Michael A. Riepe
G06 - COMPUTING CALCULATING COUNTING