John R. Abernathey

Person

Jericho, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Structure for interconnecting different polysilicon zones on semico...
- Patent number 5,672,901
- Issue date Sep 30, 1997
- International Business Machines Corporation
- John Robert Abernathey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and structure for interconnecting different polysilicon zone...
- Patent number 5,453,400
- Issue date Sep 26, 1995
- International Business Machines Corporation
- John R. Abernathey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bilayer metallization cap for photolithography
- Patent number 5,219,788
- Issue date Jun 15, 1993
- IBM Corporation
- John R. Abernathey
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method of forming metal-strapped polysilicon gate electrode for FET...
- Patent number 4,755,478
- Issue date Jul 5, 1988
- International Business Machines Corporation
- John R. Abernathey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon oxynitride storage node dielectric
- Patent number 4,725,560
- Issue date Feb 16, 1988
- International Business Machines Corp.
- John R. Abernathey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating silicon-on-insulator transistors with a share...
- Patent number 4,649,627
- Issue date Mar 17, 1987
- International Business Machines Corporation
- John R. Abernathey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of producing a thin silicon-on-insulator layer
- Patent number 4,601,779
- Issue date Jul 22, 1986
- International Business Machines Corporation
- John R. Abernathey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertically isolated complementary transistors
- Patent number 4,556,585
- Issue date Dec 3, 1985
- International Business Machines Corporation
- John R. Abernathey
- H01 - BASIC ELECTRIC ELEMENTS

John R. Abernathey

Person

Patents Grantslast 30 patents

Structure for interconnecting different polysilicon zones on semico...

Method and structure for interconnecting different polysilicon zone...

Bilayer metallization cap for photolithography

Method of forming metal-strapped polysilicon gate electrode for FET...

Silicon oxynitride storage node dielectric

Method of fabricating silicon-on-insulator transistors with a share...

Method of producing a thin silicon-on-insulator layer

Vertically isolated complementary transistors