Kamal Chaudhary

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Latch based optimization during implementation of circuit designs f...
- Patent number 8,146,041
- Issue date Mar 27, 2012
- Xilinx, Inc.
- Sankaranarayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latch based optimization during implementation of circuit designs f...
- Patent number 8,010,923
- Issue date Aug 30, 2011
- Xilinx, Inc.
- Sankaranarayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fanout-optimization during physical synthesis for placed circuit de...
- Patent number 7,853,914
- Issue date Dec 14, 2010
- Xilinx, Inc.
- Sankaranarayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placing partitioned circuit designs within iterative implementation...
- Patent number 7,590,960
- Issue date Sep 15, 2009
- Xilinx, Inc.
- Raymond Kong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Incremental placement during physical synthesis
- Patent number 7,536,661
- Issue date May 19, 2009
- Xilinx, Inc.
- Amit Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhanced incremental placement during physical synthesis
- Patent number 7,428,718
- Issue date Sep 23, 2008
- Xilinx, Inc.
- Amit Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Congestion estimation for programmable logic devices
- Patent number 7,146,590
- Issue date Dec 5, 2006
- Xilinx, Inc.
- Kamal Chaudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuits and methods for testing programmable logic devices using l...
- Patent number 7,111,214
- Issue date Sep 19, 2006
- Xilinx, Inc.
- Kamal Chaudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable circuit optionally configurable as a lookup table or a...
- Patent number 7,075,333
- Issue date Jul 11, 2006
- Xilinx, Inc.
- Kamal Chaudhary
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Relocation of components for post-placement optimization
- Patent number 7,072,815
- Issue date Jul 4, 2006
- Xilinx, Inc.
- Kamal Chaudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pin reordering during placement of circuit designs
- Patent number 7,058,915
- Issue date Jun 6, 2006
- Xilinx, Inc.
- Amit Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for automatic timing-driven implementation of...
- Patent number 6,484,298
- Issue date Nov 19, 2002
- Xilinx, Inc.
- Sudip K. Nag
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnect structure for a programmable logic device
- Patent number 6,448,808
- Issue date Sep 10, 2002
- Xilinx, Inc.
- Steven P. Young
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for analytical placement of cells using density surface repr...
- Patent number 6,415,425
- Issue date Jul 2, 2002
- Xilinx, Inc.
- Kamal Chaudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiplexer for implementing logic functions in a programmable logi...
- Patent number 6,362,648
- Issue date Mar 26, 2002
- Xilinx, Inc.
- Bernard J. New
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delay optimized mapping for programmable gate arrays with multiple...
- Patent number 6,336,208
- Issue date Jan 1, 2002
- Xilinx, Inc.
- Sundararajarao Mohan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnect structure for a programmable logic device
- Patent number 6,292,022
- Issue date Sep 18, 2001
- Xilinx, Inc.
- Steven P. Young
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
FPGA architecture with offset interconnect lines
- Patent number 6,204,690
- Issue date Mar 20, 2001
- Xilinx, Inc.
- Steven P. Young
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Wide logic gate implemented in an FPGA configurable logic element
- Patent number 6,201,410
- Issue date Mar 13, 2001
- Xilinx, Inc.
- Bernard J. New
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable logic element with ability to evaluate wide logic func...
- Patent number 6,124,731
- Issue date Sep 26, 2000
- Xilinx, Inc.
- Steven P. Young
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
FPGA CLE with two independent carry chains
- Patent number 6,107,827
- Issue date Aug 22, 2000
- Xilinx, Inc.
- Steven P. Young
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Post-placement residual overlap removal method for core-based PLD p...
- Patent number 6,086,631
- Issue date Jul 11, 2000
- Xilinx, Inc.
- Kamal Chaudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for implementing priority encoders using FPGA carry logic
- Patent number 6,081,914
- Issue date Jun 27, 2000
- Xilinx, Inc.
- Kamal Chaudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable logic element with ability to evaluate five and six in...
- Patent number 6,051,992
- Issue date Apr 18, 2000
- Xilinx, Inc.
- Steven P. Young
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable logic element with fast feedback paths
- Patent number 5,963,050
- Issue date Oct 5, 1999
- Xilinx, Inc.
- Steven P. Young
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
FPGA repeatable interconnect structure with bidirectional and unidi...
- Patent number 5,942,913
- Issue date Aug 24, 1999
- Xilinx, Inc.
- Steven P. Young
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed bus with tree structure for selecting bus driver
- Patent number 5,936,424
- Issue date Aug 10, 1999
- Xilinx, Inc.
- Steven P. Young
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable logic element with ability to evaluate five and six in...
- Patent number 5,920,202
- Issue date Jul 6, 1999
- Xilinx, Inc.
- Steven P. Young
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
FPGA repeatable interconnect structure with hierarchical interconne...
- Patent number 5,914,616
- Issue date Jun 22, 1999
- Xilinx, Inc.
- Steven P. Young
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
FPGA having logic element carry chains capable of generating wide X...
- Patent number 5,889,411
- Issue date Mar 30, 1999
- Xilinx, Inc.
- Kamal Chaudhary
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Interconnect structure for a programmable logic device
- Publication number 20020008541
- Publication date Jan 24, 2002
- Xilinx, Inc.
- Steven P. Young
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Interconnect structure for a programmable logic device
- Publication number 20010007428
- Publication date Jul 12, 2001
- Steven P. Young
- H03 - BASIC ELECTRONIC CIRCUITRY

Kamal Chaudhary

Person

Patents Grantslast 30 patents

Latch based optimization during implementation of circuit designs f...

Latch based optimization during implementation of circuit designs f...

Fanout-optimization during physical synthesis for placed circuit de...

Placing partitioned circuit designs within iterative implementation...

Incremental placement during physical synthesis

Enhanced incremental placement during physical synthesis

Congestion estimation for programmable logic devices

Circuits and methods for testing programmable logic devices using l...

Programmable circuit optionally configurable as a lookup table or a...

Relocation of components for post-placement optimization

Pin reordering during placement of circuit designs

Method and apparatus for automatic timing-driven implementation of...

Interconnect structure for a programmable logic device

Method for analytical placement of cells using density surface repr...

Multiplexer for implementing logic functions in a programmable logi...

Delay optimized mapping for programmable gate arrays with multiple...

Interconnect structure for a programmable logic device

FPGA architecture with offset interconnect lines

Wide logic gate implemented in an FPGA configurable logic element

Configurable logic element with ability to evaluate wide logic func...

FPGA CLE with two independent carry chains

Post-placement residual overlap removal method for core-based PLD p...

Method for implementing priority encoders using FPGA carry logic

Configurable logic element with ability to evaluate five and six in...

Configurable logic element with fast feedback paths

FPGA repeatable interconnect structure with bidirectional and unidi...

High speed bus with tree structure for selecting bus driver

Configurable logic element with ability to evaluate five and six in...

FPGA repeatable interconnect structure with hierarchical interconne...

FPGA having logic element carry chains capable of generating wide X...

Patents Applicationslast 30 patents

Interconnect structure for a programmable logic device

Interconnect structure for a programmable logic device