Keith A. Joyner

Person

Richardson, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for manufacturing and structure for transistors with reduced...
- Patent number 7,459,734
- Issue date Dec 2, 2008
- Texas Instruments Incorporated
- Keith A. Joyner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and apparatus for inducing stress in a semiconductor device
- Patent number 7,339,214
- Issue date Mar 4, 2008
- Texas Instruments Incorporated
- Christoph Wasshuber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Means for forming SOI
- Patent number 7,101,772
- Issue date Sep 5, 2006
- Texas Instruments Incorporated
- Theodore W. Houston
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and apparatus for inducing stress in a semiconductor device
- Patent number 6,806,151
- Issue date Oct 19, 2004
- Texas Instruments Incorporated
- Christoph Wasshuber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing and structure for transistors with reduced...
- Patent number 6,767,777
- Issue date Jul 27, 2004
- Texas Instruments Incorporated
- Keith A. Joyner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with fully self-aligned local interconnects, a...
- Patent number 6,737,347
- Issue date May 18, 2004
- Texas Instruments Incorporated
- Theodore W. Houston
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Variable porosity porous silicon isolation
- Patent number 6,376,859
- Issue date Apr 23, 2002
- Texas Instruments Incorporated
- Leland S. Swanson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Annealed porous silicon with epitaxial layer for SOI
- Patent number 6,376,285
- Issue date Apr 23, 2002
- Texas Instruments Incorporated
- Keith A. Joyner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Organic sidewall spacers used with resist
- Patent number 6,228,747
- Issue date May 8, 2001
- Texas Instruments Incorporated
- Keith A. Joyner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming an isolation structure in a substrate
- Patent number 6,214,699
- Issue date Apr 10, 2001
- Texas Instruments Incorporated
- Keith A. Joyner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned trenched-channel lateral-current-flow transistor
- Patent number 6,207,511
- Issue date Mar 27, 2001
- Texas Instruments Incorporated
- Richard A. Chapman
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Isolation structure and method
- Patent number 6,180,491
- Issue date Jan 30, 2001
- Texas Instruments Incorporated
- Keith A. Joyner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Uniform dopant distribution for mesas of semiconductors
- Patent number 6,171,969
- Issue date Jan 9, 2001
- Texas Instruments Incorporated
- Keith A. Joyner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned trenched-channel lateral-current-flow transistor
- Patent number 6,118,161
- Issue date Sep 12, 2000
- Texas Instruments Incorporated
- Richard A. Chapman
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Trench isolation of a CMOS structure
- Patent number 6,114,741
- Issue date Sep 5, 2000
- Texas Instruments Incorporated
- Keith A. Joyner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon-on-insulation trench isolation structure and method for for...
- Patent number 6,057,214
- Issue date May 2, 2000
- Texas Instruments Incorporated
- Keith A. Joyner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Implant enhancement of titanium silicidation
- Patent number 6,004,871
- Issue date Dec 21, 1999
- Texas Instruments Incorporated
- Jorge Adrian Kittl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Active silicon-on-insulator region having a buried insulation layer...
- Patent number 5,982,006
- Issue date Nov 9, 1999
- Texas Instruments Incorporated
- Keith A. Joyner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reducing non-uniformity in a refill layer thickness for a semicondu...
- Patent number 5,909,628
- Issue date Jun 1, 1999
- Texas Instruments Incorporated
- Amitava Chatterjee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Mesa isolation Refill Process for Silicon on Insulator Technology U...
- Patent number 5,882,981
- Issue date Mar 16, 1999
- Texas Instruments Incorporated
- Rajan Rajgopal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Oxide deglaze before sidewall oxidation of mesa or trench
- Patent number 5,863,827
- Issue date Jan 26, 1999
- Texas Instruments Incorporated
- Keith Joyner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Varying the thickness of the surface silicon layer in a silicon-on-...
- Patent number 5,548,149
- Issue date Aug 20, 1996
- Texas Instruments Incorporated
- Keith A. Joyner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems and methods for controlling the temperature and uniformity...
- Patent number 5,440,132
- Issue date Aug 8, 1995
- Texas Instruments Incorporated
- Keith A. Joyner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for constructing semiconductor-on-insulator
- Patent number 5,429,955
- Issue date Jul 4, 1995
- Texas Instruments Incorporated
- Keith A. Joyner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Varying the thickness of the surface silicon layer in a silicon-on-...
- Patent number 5,364,800
- Issue date Nov 15, 1994
- Texas Instruments Incorporated
- Keith A. Joyner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reducing leakage current in silicon-on-insulator substrates
- Patent number 5,352,341
- Issue date Oct 4, 1994
- Texas Instruments Incorporated
- Keith A. Joyner
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Grant
Process for forming an electrical interconnection system on a semic...
- Patent number 4,507,851
- Issue date Apr 2, 1985
- Texas Instruments Incorporated
- Keith A. Joyner
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...

Patents Applicationslast 30 patents

Information Patent Application
Methods and apparatus for inducing stress in a semiconductor device
- Publication number 20050029560
- Publication date Feb 10, 2005
- Christoph Wasshuber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for manufacturing and structure for transistors with reduced...
- Publication number 20040211992
- Publication date Oct 28, 2004
- Keith A. Joyner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device with fully self-aligned local interconnects, a...
- Publication number 20040192027
- Publication date Sep 30, 2004
- Theodore W. Houston
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process to improve Nwell-Nwell isolation with a blanket low dose hi...
- Publication number 20040169236
- Publication date Sep 2, 2004
- TEXAS INSTRUMENTS INCORPORATED
- Seetharaman Sridhar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods and apparatus for inducing stress in a semiconductor device
- Publication number 20030111699
- Publication date Jun 19, 2003
- Christoph Wasshuber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for manufacturing and structure for transistors with reduced...
- Publication number 20020106875
- Publication date Aug 8, 2002
- Keith A. Joyner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process to improve Nwell-Nwell isolation with a blanket low dose hi...
- Publication number 20020086499
- Publication date Jul 4, 2002
- Seetharaman Sridhar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Means for forming SOI
- Publication number 20020086463
- Publication date Jul 4, 2002
- Theodore W. Houston
- H01 - BASIC ELECTRIC ELEMENTS

Keith A. Joyner

Person

Patents Grantslast 30 patents

Method for manufacturing and structure for transistors with reduced...

Methods and apparatus for inducing stress in a semiconductor device

Means for forming SOI

Methods and apparatus for inducing stress in a semiconductor device

Method for manufacturing and structure for transistors with reduced...

Semiconductor device with fully self-aligned local interconnects, a...

Variable porosity porous silicon isolation

Annealed porous silicon with epitaxial layer for SOI

Organic sidewall spacers used with resist

Method for forming an isolation structure in a substrate

Self-aligned trenched-channel lateral-current-flow transistor

Isolation structure and method

Uniform dopant distribution for mesas of semiconductors

Self-aligned trenched-channel lateral-current-flow transistor

Trench isolation of a CMOS structure

Silicon-on-insulation trench isolation structure and method for for...

Implant enhancement of titanium silicidation

Active silicon-on-insulator region having a buried insulation layer...

Reducing non-uniformity in a refill layer thickness for a semicondu...

Mesa isolation Refill Process for Silicon on Insulator Technology U...

Oxide deglaze before sidewall oxidation of mesa or trench

Varying the thickness of the surface silicon layer in a silicon-on-...

Systems and methods for controlling the temperature and uniformity...

Method for constructing semiconductor-on-insulator

Varying the thickness of the surface silicon layer in a silicon-on-...

Reducing leakage current in silicon-on-insulator substrates

Process for forming an electrical interconnection system on a semic...

Patents Applicationslast 30 patents

Methods and apparatus for inducing stress in a semiconductor device

Method for manufacturing and structure for transistors with reduced...

Semiconductor device with fully self-aligned local interconnects, a...

Process to improve Nwell-Nwell isolation with a blanket low dose hi...

Methods and apparatus for inducing stress in a semiconductor device

Method for manufacturing and structure for transistors with reduced...

Process to improve Nwell-Nwell isolation with a blanket low dose hi...

Means for forming SOI