Kuang-Yeh Chang

Person

Los Gatos, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for forming an integrated circuit having improved polysilico...
- Patent number 6,300,180
- Issue date Oct 9, 2001
- Advanced Micro Devices, Inc.
- Kuang-Yeh Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low voltage CMOS process and device with individually adjustable LD...
- Patent number 6,222,238
- Issue date Apr 24, 2001
- VLSI Technology, Inc.
- Kuang-Yeh Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming low resistance contact structures in vias arrange...
- Patent number 6,013,574
- Issue date Jan 11, 2000
- Advanced Micro Devices, Inc.
- Fred N. Hause
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduced bird's beak field oxidation process using nitrogen implante...
- Patent number 5,962,914
- Issue date Oct 5, 1999
- Advanced Micro Devices, Inc.
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Advanced isolation scheme for deep submicron technology
- Patent number 5,950,097
- Issue date Sep 7, 1999
- Advanced Micro Devices, Inc.
- Kuang-Yeh Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduced bird's beak field oxidation process using nitrogen implante...
- Patent number 5,937,310
- Issue date Aug 10, 1999
- Advanced Micro Devices, Inc.
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making SRAM cell having single layer polysilicon thin fil...
- Patent number 5,904,512
- Issue date May 18, 1999
- Advanced Micro Devices, Inc.
- Kuang-Yeh Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor trench isolation process resulting in a silicon mesa...
- Patent number 5,904,539
- Issue date May 18, 1999
- Advanced Micro Devices, Inc.
- Fred N. Hause
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming advanced transistor structures with optimum shor...
- Patent number 5,877,049
- Issue date Mar 2, 1999
- Advanced Micro Devices, Inc.
- Yowjuang W. Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reverse CMOS method for dual isolation semiconductor device
- Patent number 5,874,328
- Issue date Feb 23, 1999
- Advanced Micro Devices, Inc.
- Yowjuang W. Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit having improved polysilicon resistor structures
- Patent number 5,838,044
- Issue date Nov 17, 1998
- Advanced Micro Devices
- Kuang-Yeh Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating FET or CMOS transistors using MeV implantation
- Patent number 5,821,146
- Issue date Oct 13, 1998
- Advanced Micro Devices, Inc.
- Kuang-Yeh Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nitrogenated trench liner for improved shallow trench isolation
- Patent number 5,811,347
- Issue date Sep 22, 1998
- Advanced Micro Devices, Inc.
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low voltage CMOS process with individually adjustable LDD spacers
- Patent number 5,786,247
- Issue date Jul 28, 1998
- VLSI Technology, Inc.
- Kuang-Yeh Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device reliability of MOS devices using silicon rich plasma oxide f...
- Patent number 5,763,937
- Issue date Jun 9, 1998
- VLSI Technology, Inc.
- Vivek Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SRAM cell having single layer polysilicon thin film transistors
- Patent number 5,734,179
- Issue date Mar 31, 1998
- Advanced Micro Devices, Inc.
- Kuang-Yeh Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making via structure with metallic spacer
- Patent number 5,712,195
- Issue date Jan 27, 1998
- VLSI Technology, Inc.
- Kuang-Yeh Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reverse damascene via structures
- Patent number 5,693,568
- Issue date Dec 2, 1997
- Advanced Micro Devices, Inc.
- Yowjuang W. Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit isolation process
- Patent number 5,643,825
- Issue date Jul 1, 1997
- Advanced Micro Devices, Inc.
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating field effect transistors having lightly doped...
- Patent number 5,610,088
- Issue date Mar 11, 1997
- Advanced Micro Devices, Inc.
- Kuang-Yeh Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Advanced transistor structures with optimum short channel controls...
- Patent number 5,608,253
- Issue date Mar 4, 1997
- Advanced Micro Devices Inc.
- Yowjuang W. Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming reliable MOS devices using silicon rich plasma o...
- Patent number 5,602,056
- Issue date Feb 11, 1997
- VLSI Technology, Inc.
- Vivek Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making flash memory cell
- Patent number 5,587,332
- Issue date Dec 24, 1996
- VLSI Technology, Inc.
- Kuang-Yeh Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-level antifuse structure
- Patent number 5,565,703
- Issue date Oct 15, 1996
- VLSI Technology, Inc.
- Kuang-Yeh Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Advanced isolation scheme for deep submicron technology
- Patent number 5,554,562
- Issue date Sep 10, 1996
- Advanced Micro Devices, Inc.
- Kuang-Yeh Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lightly doped drain profile optimization with high energy implants
- Patent number 5,512,506
- Issue date Apr 30, 1996
- Advanced Micro Devices, Inc.
- Kuang-Yeh Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS locos isolation for self-aligned NPN BJT in a BiCMOS process
- Patent number 5,504,364
- Issue date Apr 2, 1996
- VLSI Technology, Inc.
- Kuang-Yeh Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit contact barrier formation with ion implant
- Patent number 5,493,132
- Issue date Feb 20, 1996
- VLSI Technology, Inc.
- Hunter B. Brugge
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Conductive via structure for integrated circuits and method for mak...
- Patent number 5,493,152
- Issue date Feb 20, 1996
- VLSI Technology, Inc.
- Kuang-Yeh Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making structure for suppression of field inversion cause...
- Patent number 5,492,865
- Issue date Feb 20, 1996
- VLSI Technology, Inc.
- Subhash R. Nariani
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
NITROGENATED TRENCH LINER FOR IMPROVED SHALLOW TRENCH ISOLATION
- Publication number 20010001723
- Publication date May 24, 2001
- MARK I. GARDNER
- H01 - BASIC ELECTRIC ELEMENTS

Kuang-Yeh Chang

Person

Patents Grantslast 30 patents

Method for forming an integrated circuit having improved polysilico...

Low voltage CMOS process and device with individually adjustable LD...

Method of forming low resistance contact structures in vias arrange...

Reduced bird's beak field oxidation process using nitrogen implante...

Advanced isolation scheme for deep submicron technology

Reduced bird's beak field oxidation process using nitrogen implante...

Method of making SRAM cell having single layer polysilicon thin fil...

Semiconductor trench isolation process resulting in a silicon mesa...

Method for forming advanced transistor structures with optimum shor...

Reverse CMOS method for dual isolation semiconductor device

Integrated circuit having improved polysilicon resistor structures

Method of fabricating FET or CMOS transistors using MeV implantation

Nitrogenated trench liner for improved shallow trench isolation

Low voltage CMOS process with individually adjustable LDD spacers

Device reliability of MOS devices using silicon rich plasma oxide f...

SRAM cell having single layer polysilicon thin film transistors

Method for making via structure with metallic spacer

Reverse damascene via structures

Integrated circuit isolation process

Method of fabricating field effect transistors having lightly doped...

Advanced transistor structures with optimum short channel controls...

Method for forming reliable MOS devices using silicon rich plasma o...

Method of making flash memory cell

Multi-level antifuse structure

Advanced isolation scheme for deep submicron technology

Lightly doped drain profile optimization with high energy implants

CMOS locos isolation for self-aligned NPN BJT in a BiCMOS process

Integrated circuit contact barrier formation with ion implant

Conductive via structure for integrated circuits and method for mak...

Method of making structure for suppression of field inversion cause...

Patents Applicationslast 30 patents

NITROGENATED TRENCH LINER FOR IMPROVED SHALLOW TRENCH ISOLATION