Kumar Venkatramani

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Adaptable circuit blocks for use in multi-block chip design
- Patent number 7,249,340
- Issue date Jul 24, 2007
- Cadence Design Systems, Inc.
- Laurence H. Cooke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Block based design methodology with programmable components
- Patent number 6,968,514
- Issue date Nov 22, 2005
- Cadence Design Systems, Inc.
- Laurence H. Cooke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptable circuit blocks for use in multi-block chip design
- Patent number 6,901,562
- Issue date May 31, 2005
- Cadence Design Systems, Inc.
- Laurence H. Cooke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Blocked based design methodology
- Patent number 6,725,432
- Issue date Apr 20, 2004
- Cadence Design Systems, Inc.
- Henry Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Block based design methodology
- Patent number 6,701,504
- Issue date Mar 2, 2004
- Cadence Design Systems, Inc.
- Henry Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Blocked based design methodology
- Patent number 6,698,002
- Issue date Feb 24, 2004
- Cadence Design Systems, Inc.
- Henry Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Block based design methodology
- Patent number 6,694,501
- Issue date Feb 17, 2004
- Cadence Design Systems, Inc.
- Henry Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for H-Tree clocking layout
- Patent number 6,651,237
- Issue date Nov 18, 2003
- Cadence Design Systems, Inc.
- Laurence H. Cooke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Block based design methodology
- Patent number 6,631,470
- Issue date Oct 7, 2003
- Cadence Design Systems, Inc.
- Henry Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Block based design methodology
- Patent number 6,629,293
- Issue date Sep 30, 2003
- Cadence Design Systems, Inc.
- Henry Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Block based design methodology
- Patent number 6,594,800
- Issue date Jul 15, 2003
- Cadence Design Systems, Inc.
- Henry Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Block based design methodology
- Patent number 6,574,778
- Issue date Jun 3, 2003
- Cadence Design Systems, Inc.
- Henry Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Block based design methodology
- Patent number 6,567,957
- Issue date May 20, 2003
- Cadence Design Systems, Inc.
- Henry Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Block based design methodology
- Patent number 6,269,467
- Issue date Jul 31, 2001
- Cadence Design Systems, Inc.
- Henry Chang
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Adaptable circuit blocks for use in multi-block chip design
- Publication number 20050066295
- Publication date Mar 24, 2005
- Cadence Design Systems, Inc.
- Laurence H. Cooke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Block based design methodology
- Publication number 20030115564
- Publication date Jun 19, 2003
- Cadence Design Systems, Inc.
- Henry Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Block based design methodology
- Publication number 20020166098
- Publication date Nov 7, 2002
- Cadence Design Systems, Inc.
- Henry Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Block based design methodology with programmable components
- Publication number 20020073380
- Publication date Jun 13, 2002
- Cadence Design Systems, Inc.
- Laurence H. Cooke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Block based design methodology
- Publication number 20020016952
- Publication date Feb 7, 2002
- Cadence Design Systems, Inc.
- Henry Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Block based design methodology
- Publication number 20010042237
- Publication date Nov 15, 2001
- Cadence Design Systems, Inc.
- Henry Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Block based design methodology
- Publication number 20010039641
- Publication date Nov 8, 2001
- Cadence Design Systems, Inc.
- Henry Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adaptable circuit blocks for use in multi-block chip design
- Publication number 20010034593
- Publication date Oct 25, 2001
- Laurence H. Cooke
- G01 - MEASURING TESTING
Information Patent Application
System and method for H-Tree clocking layout
- Publication number 20010025368
- Publication date Sep 27, 2001
- Cadence Design Systems, Inc.
- Laurence H. Cooke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Block based design methodology
- Publication number 20010025369
- Publication date Sep 27, 2001
- Cadence Design Systems, Inc.
- Henry Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Block based design methodology
- Publication number 20010018756
- Publication date Aug 30, 2001
- Cadence Design Systems, Inc.
- Henry Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Block based design methodology
- Publication number 20010016933
- Publication date Aug 23, 2001
- Cadence Design Systems, Inc.
- Henry Chang
- G06 - COMPUTING CALCULATING COUNTING

Kumar Venkatramani

Person

Patents Grantslast 30 patents

Adaptable circuit blocks for use in multi-block chip design

Block based design methodology with programmable components

Adaptable circuit blocks for use in multi-block chip design

Blocked based design methodology

Block based design methodology

Blocked based design methodology

Block based design methodology

System and method for H-Tree clocking layout

Block based design methodology

Block based design methodology

Block based design methodology

Block based design methodology

Block based design methodology

Block based design methodology

Patents Applicationslast 30 patents

Adaptable circuit blocks for use in multi-block chip design

Block based design methodology

Block based design methodology

Block based design methodology with programmable components

Block based design methodology

Block based design methodology

Block based design methodology

Adaptable circuit blocks for use in multi-block chip design

System and method for H-Tree clocking layout

Block based design methodology

Block based design methodology

Block based design methodology