Luu Nguyen

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Bump bond structure for enhanced electromigration performance
- Patent number 11,450,638
- Issue date Sep 20, 2022
- Texas Instruments Incorporated
- Dibyajat Mishra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fan-out electronic device
- Patent number 11,410,875
- Issue date Aug 9, 2022
- Texas Instruments Incorporated
- Hau Thanh Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit backside metallization
- Patent number 11,367,699
- Issue date Jun 21, 2022
- Texas Instruments Incorporated
- Hiroyuki Sada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D-printed protective shell structures with support columns for str...
- Patent number 11,082,028
- Issue date Aug 3, 2021
- Texas Instruments Incorporated
- James Cooper Wainerdi
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Packaged semiconductor device with multilayer stress buffer
- Patent number 11,031,311
- Issue date Jun 8, 2021
- Texas Instruments Incorporated
- Luu Thanh Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Copper passivation
- Patent number 11,021,786
- Issue date Jun 1, 2021
- Texas Instruments Incorporated
- Luu Thanh Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit backside metallization
- Patent number 10,763,230
- Issue date Sep 1, 2020
- Texas Instruments Incorporated
- Hiroyuki Sada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bump bond structure for enhanced electromigration performance
- Patent number 10,763,231
- Issue date Sep 1, 2020
- Texas Instruments Incorporated
- Dibyajat Mishra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Additive deposition low temperature curable magnetic interconnectin...
- Patent number 10,650,957
- Issue date May 12, 2020
- Texas Instruments Incorporated
- Yi Yan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Printed repassivation for wafer chip scale packaging
- Patent number 10,541,220
- Issue date Jan 21, 2020
- Texas Instruments Incorporated
- Daiki Komatsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D-printed protective shell structures for stress sensitive circuits
- Patent number 10,516,381
- Issue date Dec 24, 2019
- Texas Instruments Incorporated
- James Cooper Wainerdi
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Integrated circuit package with sensor and method of making
- Patent number 10,077,186
- Issue date Sep 18, 2018
- Texas Instruments Incorporated
- Makoto Shibuya
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Integrated circuit package with sensor and method of making
- Patent number 9,688,530
- Issue date Jun 27, 2017
- Texas Instruments Incorporated
- Makoto Shibuya
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Open cavity package using chip-embedding technology
- Patent number 9,663,357
- Issue date May 30, 2017
- Texas Instruments Incorporated
- Jie Mao
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Thermally efficient integrated circuit package
- Patent number 8,716,830
- Issue date May 6, 2014
- Texas Instruments Incorporated
- Anindya Poddar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Inkjet printed leadframe
- Patent number 7,824,963
- Issue date Nov 2, 2010
- National Semiconductor Corporation
- Randall L. Walberg
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Leadframe having die attach pad with delamination and crack-arresti...
- Patent number 7,808,089
- Issue date Oct 5, 2010
- National Semiconductor Corporation
- Luu T. Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Molded optical package with fiber coupling feature
- Patent number 7,728,399
- Issue date Jun 1, 2010
- National Semiconductor Corporation
- Randall L. Walberg
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level optoelectronic package with fiber side insertion
- Patent number 7,703,993
- Issue date Apr 27, 2010
- National Semiconductor Corporation
- Artur Darbinyan
- G02 - OPTICS
Information Patent Grant
Inkjet printed leadframes
- Patent number 7,667,304
- Issue date Feb 23, 2010
- National Semiconductor Corporation
- Randall L. Walberg
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package with stress reduction
- Patent number 7,651,891
- Issue date Jan 26, 2010
- National Semiconductor Corporation
- Luu Thanh Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Optical sub-assembly packaging techniques that incorporate optical...
- Patent number 7,431,516
- Issue date Oct 7, 2008
- National Semiconductor Corporation
- William Paul Mazotti
- G02 - OPTICS
Information Patent Grant
Two-layer electrical substrate for optical devices
- Patent number 7,432,575
- Issue date Oct 7, 2008
- National Semiconductor Corporation
- Neeraj Anil Pendse
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Ceramic optical sub-assembly for optoelectronic modules
- Patent number 7,269,027
- Issue date Sep 11, 2007
- National Semiconductor Corporation
- Jia Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for forming an underfill adhesive layer
- Patent number 7,253,078
- Issue date Aug 7, 2007
- National Semiconductor Corporation
- Luu T. Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for joining an opto-electronic module to a semiconductor...
- Patent number 7,247,942
- Issue date Jul 24, 2007
- National Semiconductor Corporation
- Luu Thanh Nguyen
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Techniques for joining an opto-electronic module to a semiconductor...
- Patent number 7,199,440
- Issue date Apr 3, 2007
- National Semiconductor Corporation
- Luu Thanh Nguyen
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Technique for protecting photonic devices in optoelectronic package...
- Patent number 7,195,955
- Issue date Mar 27, 2007
- National Semiconductor Corporation
- Luu Thanh Nguyen
- B29 - WORKING OF PLASTICS WORKING OF SUBSTANCES IN A PLASTIC STATE, IN GENERAL
Information Patent Grant
Electrical interconnect with minimal parasitic capacitance
- Patent number 7,098,540
- Issue date Aug 29, 2006
- National Semiconductor Corporation
- Jitendra Mohan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Optical sub-assembly for opto-electronic modules
- Patent number 7,086,788
- Issue date Aug 8, 2006
- National Semiconductor Corporation
- William Paul Mazotti
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
Packaged Semiconductor Device With Multilayer Stress Buffer
- Publication number 20210351098
- Publication date Nov 11, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Luu Thanh Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT BACKSIDE METALLIZATION
- Publication number 20210035932
- Publication date Feb 4, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Hiroyuki SADA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BUMP BOND STRUCTURE FOR ENHANCED ELECTROMIGRATION PERFORMANCE
- Publication number 20200402938
- Publication date Dec 24, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Dibyajat Mishra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REPASSIVATION APPLICATION FOR WAFER-LEVEL CHIP-SCALE PACKAGE
- Publication number 20200388508
- Publication date Dec 10, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Makoto Shibuya
- B05 - SPRAYING OR ATOMISING IN GENERAL APPLYING LIQUIDS OR OTHER FLUENT MATER...
Information Patent Application
FAN-OUT ELECTRONIC DEVICE
- Publication number 20200203219
- Publication date Jun 25, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Hau Thanh Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT BACKSIDE METALLIZATION
- Publication number 20200203295
- Publication date Jun 25, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Hiroyuki SADA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COPPER PASSIVATION
- Publication number 20200173013
- Publication date Jun 4, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Luu Thanh Nguyen
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
PACKAGED SEMICONDUCTOR DEVICE WITH MULTILAYER STRESS BUFFER
- Publication number 20200161205
- Publication date May 21, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Luu Thanh Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADDITIVE DEPOSITION LOW TEMPERATURE CURABLE MAGNETIC INTERCONNECTIN...
- Publication number 20200135381
- Publication date Apr 30, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Yi YAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D PRINTING OF PROTECTIVE SHELL STRUCTURES FOR STRESS SENSITIVE CIR...
- Publication number 20200127637
- Publication date Apr 23, 2020
- TEXAS INSTRUMENTS INCORPORATED
- James Cooper WAINERDI
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
INKJET PRINTED ELECTRONIC COMPONENTS
- Publication number 20200105453
- Publication date Apr 2, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Yi YAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PRINTED REPASSIVATION FOR WAFER CHIP SCALE PACKAGING
- Publication number 20200043878
- Publication date Feb 6, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Daiki Komatsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BUMP BOND STRUCTURE FOR ENHANCED ELECTROMIGRATION PERFORMANCE
- Publication number 20200035633
- Publication date Jan 30, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Dibyajat Mishra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D PRINTING OF PROTECTIVE SHELL STRUCTURES FOR STRESS SENSITIVE CIR...
- Publication number 20190207582
- Publication date Jul 4, 2019
- TEXAS INSTRUMENTS INCORPORATED
- James Cooper WAINERDI
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
Integrated Circuit Package with Sensor and Method of Making
- Publication number 20170253476
- Publication date Sep 7, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Makoto Shibuya
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
OPEN CAVITY PACKAGE USING CHIP-EMBEDDING TECHNOLOGY
- Publication number 20170015548
- Publication date Jan 19, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Jie Mao
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
INTEGRATED CIRCUIT PACKAGE WITH SENSOR AND METHOD OF MAKING
- Publication number 20160347607
- Publication date Dec 1, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Makoto Shibuya
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
THERMALLY EFFICIENT INTEGRATED CIRCUIT PACKAGE
- Publication number 20130127008
- Publication date May 23, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Anindya Poddar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Bonded Semiconductor Structure With Pyramid-Shaped Alignment Openin...
- Publication number 20120217610
- Publication date Aug 30, 2012
- Peter J. Hopper
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WIREBONDING METHOD AND DEVICE ENABLING HIGH-SPEED REVERSE WEDGE BON...
- Publication number 20120032354
- Publication date Feb 9, 2012
- National Semiconductor Corporation
- Ken Pham
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
WAFER LEVEL METHOD OF FORMING SIDE FIBER INSERTION OPTOELECTRONIC P...
- Publication number 20100151614
- Publication date Jun 17, 2010
- National Semiconductor Corporation
- Artur DARBINYAN
- G02 - OPTICS
Information Patent Application
INKJET PRINTED LEADFRAME
- Publication number 20100072613
- Publication date Mar 25, 2010
- National Semiconductor Corporation
- Randall L. Walberg
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MOLDED OPTICAL PACKAGE WITH FIBER COUPLING FEATURE
- Publication number 20100019339
- Publication date Jan 28, 2010
- National Semiconductor Corporation
- Randall L. WALBERG
- G02 - OPTICS
Information Patent Application
METHODS AND SYSTEMS FOR PACKAGING INTEGRATED CIRCUITS WITH THIN MET...
- Publication number 20100015329
- Publication date Jan 21, 2010
- National Semiconductor Corporation
- Luu T. NGUYEN
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
INKJET PRINTED LEADFRAMES
- Publication number 20090267216
- Publication date Oct 29, 2009
- National Semiconductor Corporation
- Randall L. Walberg
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
I/O PAD STRUCTURE FOR ENHANCING SOLDER JOINT RELIABILITY IN INTEGRA...
- Publication number 20090174069
- Publication date Jul 9, 2009
- National Semiconductor Corporation
- Hau Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ROUNDED DIE CONFIGURATION FOR STRESS MINIMIZATION AND ENHANCED THER...
- Publication number 20090152683
- Publication date Jun 18, 2009
- National Semiconductor Corporation
- Luu T. Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LEADFRAME HAVING DIE ATTACH PAD WITH DELAMINATION AND CRACK-ARRESTI...
- Publication number 20090152691
- Publication date Jun 18, 2009
- National Semiconductor Corporation
- Luu T. Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Optical sub-assembly packaging techniques that incorporate optical...
- Publication number 20070071391
- Publication date Mar 29, 2007
- National Semiconductor Corporation
- William Paul Mazotti
- G02 - OPTICS
Information Patent Application
Ceramic optical sub-assembly for optoelectronic modules
- Publication number 20060140534
- Publication date Jun 29, 2006
- National Semiconductor Corporation
- Jia Liu
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Bump bond structure for enhanced electromigration performance

Fan-out electronic device

Integrated circuit backside metallization

3D-printed protective shell structures with support columns for str...

Packaged semiconductor device with multilayer stress buffer

Copper passivation

Integrated circuit backside metallization

Bump bond structure for enhanced electromigration performance

Additive deposition low temperature curable magnetic interconnectin...

Printed repassivation for wafer chip scale packaging

3D-printed protective shell structures for stress sensitive circuits

Integrated circuit package with sensor and method of making

Integrated circuit package with sensor and method of making

Open cavity package using chip-embedding technology

Thermally efficient integrated circuit package

Inkjet printed leadframe

Leadframe having die attach pad with delamination and crack-arresti...

Molded optical package with fiber coupling feature

Wafer level optoelectronic package with fiber side insertion

Inkjet printed leadframes

Integrated circuit package with stress reduction

Optical sub-assembly packaging techniques that incorporate optical...

Two-layer electrical substrate for optical devices

Ceramic optical sub-assembly for optoelectronic modules

Method and apparatus for forming an underfill adhesive layer

Techniques for joining an opto-electronic module to a semiconductor...

Techniques for joining an opto-electronic module to a semiconductor...

Technique for protecting photonic devices in optoelectronic package...

Electrical interconnect with minimal parasitic capacitance

Optical sub-assembly for opto-electronic modules

Patents Applicationslast 30 patents

Packaged Semiconductor Device With Multilayer Stress Buffer

INTEGRATED CIRCUIT BACKSIDE METALLIZATION

BUMP BOND STRUCTURE FOR ENHANCED ELECTROMIGRATION PERFORMANCE

REPASSIVATION APPLICATION FOR WAFER-LEVEL CHIP-SCALE PACKAGE

FAN-OUT ELECTRONIC DEVICE

INTEGRATED CIRCUIT BACKSIDE METALLIZATION

COPPER PASSIVATION

PACKAGED SEMICONDUCTOR DEVICE WITH MULTILAYER STRESS BUFFER

ADDITIVE DEPOSITION LOW TEMPERATURE CURABLE MAGNETIC INTERCONNECTIN...

3D PRINTING OF PROTECTIVE SHELL STRUCTURES FOR STRESS SENSITIVE CIR...

INKJET PRINTED ELECTRONIC COMPONENTS

PRINTED REPASSIVATION FOR WAFER CHIP SCALE PACKAGING

BUMP BOND STRUCTURE FOR ENHANCED ELECTROMIGRATION PERFORMANCE

3D PRINTING OF PROTECTIVE SHELL STRUCTURES FOR STRESS SENSITIVE CIR...

Integrated Circuit Package with Sensor and Method of Making

OPEN CAVITY PACKAGE USING CHIP-EMBEDDING TECHNOLOGY

INTEGRATED CIRCUIT PACKAGE WITH SENSOR AND METHOD OF MAKING

THERMALLY EFFICIENT INTEGRATED CIRCUIT PACKAGE

Bonded Semiconductor Structure With Pyramid-Shaped Alignment Openin...

WIREBONDING METHOD AND DEVICE ENABLING HIGH-SPEED REVERSE WEDGE BON...

WAFER LEVEL METHOD OF FORMING SIDE FIBER INSERTION OPTOELECTRONIC P...

INKJET PRINTED LEADFRAME

MOLDED OPTICAL PACKAGE WITH FIBER COUPLING FEATURE

METHODS AND SYSTEMS FOR PACKAGING INTEGRATED CIRCUITS WITH THIN MET...

INKJET PRINTED LEADFRAMES

I/O PAD STRUCTURE FOR ENHANCING SOLDER JOINT RELIABILITY IN INTEGRA...

ROUNDED DIE CONFIGURATION FOR STRESS MINIMIZATION AND ENHANCED THER...

LEADFRAME HAVING DIE ATTACH PAD WITH DELAMINATION AND CRACK-ARRESTI...

Optical sub-assembly packaging techniques that incorporate optical...

Ceramic optical sub-assembly for optoelectronic modules