Marc E. Levitt

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for ensuring mutual exclusivity of selected signals during a...
- Patent number 6,081,913
- Issue date Jun 27, 2000
- Sun Microsystems, Inc.
- Sridhar Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Clock stopping schemes for data buffer
- Patent number 5,900,757
- Issue date May 4, 1999
- Sun Microsystems, Inc.
- Sandeep K. Aggarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mutual exclusivity circuit for use in test pattern application scan...
- Patent number 5,898,702
- Issue date Apr 27, 1999
- Sun Microsystems, Inc.
- Sridhar Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Boundary-scan circuit for use with linearized impedance control typ...
- Patent number 5,892,778
- Issue date Apr 6, 1999
- Sun Microsystems, Inc.
- Farideh Golshan
- G01 - MEASURING TESTING
Information Patent Grant
Method for interfacing boundary-scan circuitry with linearized impe...
- Patent number 5,872,796
- Issue date Feb 16, 1999
- Sun Microsystems, Inc.
- Farideh Golshan
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for on die testing
- Patent number 5,870,408
- Issue date Feb 9, 1999
- Sun Microsystems, Inc.
- Sandeep K. Aggarwal
- G01 - MEASURING TESTING
Information Patent Grant
Control circuit for deterministic stopping of an integrated circuit...
- Patent number 5,864,564
- Issue date Jan 26, 1999
- Sun Microsystems, Inc.
- Marc E. Levitt
- G01 - MEASURING TESTING
Information Patent Grant
Final stage clock buffer in a clock distribution network
- Patent number 5,850,150
- Issue date Dec 15, 1998
- Sun Microsystems, Inc.
- Sundari S. Mitra
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit with identification signal writing circuitry dis...
- Patent number 5,787,012
- Issue date Jul 28, 1998
- Sun Microsystems, Inc.
- Marc E. Levitt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipelined scan enable for fast scan testing
- Patent number 5,774,474
- Issue date Jun 30, 1998
- Sun Microsystems, Inc.
- Sridhar Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for identifying faults within a system
- Patent number 5,570,376
- Issue date Oct 29, 1996
- Sun Microsystems, Inc.
- Ramachandra P. Kunda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic signal validity verification apparatus
- Patent number 5,528,165
- Issue date Jun 18, 1996
- Sun Microsystems, Inc.
- Slobodan Simovich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for interconnect testing without speed degrada...
- Patent number 5,513,186
- Issue date Apr 30, 1996
- Sun Microsystems, Inc.
- Marc E. Levitt
- G01 - MEASURING TESTING
Information Patent Grant
Maximizing improvement to fault coverage of system logic of an inte...
- Patent number 5,379,303
- Issue date Jan 3, 1995
- Sun Microsystems, Inc.
- Marc E. Levitt
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for improving fault coverage of system logic o...
- Patent number 5,341,382
- Issue date Aug 23, 1994
- Sun Microsystems, Inc.
- Marc E. Levitt
- G06 - COMPUTING CALCULATING COUNTING

Marc E. Levitt

Person

Patents Grantslast 30 patents

Method for ensuring mutual exclusivity of selected signals during a...

Clock stopping schemes for data buffer

Mutual exclusivity circuit for use in test pattern application scan...

Boundary-scan circuit for use with linearized impedance control typ...

Method for interfacing boundary-scan circuitry with linearized impe...

Method and apparatus for on die testing

Control circuit for deterministic stopping of an integrated circuit...

Final stage clock buffer in a clock distribution network

Integrated circuit with identification signal writing circuitry dis...

Pipelined scan enable for fast scan testing

Method and apparatus for identifying faults within a system

Logic signal validity verification apparatus

Method and apparatus for interconnect testing without speed degrada...

Maximizing improvement to fault coverage of system logic of an inte...

Method and apparatus for improving fault coverage of system logic o...