Marek Hytha

Person

Brookline, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for making semiconductor device including a superlattice and...
- Patent number 12,322,594
- Issue date Jun 3, 2025
- ATOMERA INCORPORATED
- Marek Hytha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making semiconductor device with selective etching of su...
- Patent number 12,315,723
- Issue date May 27, 2025
- ATOMERA INCORPORATED
- Marek Hytha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including superlattice with O18 enriched monol...
- Patent number 12,199,148
- Issue date Jan 14, 2025
- ATOMERA INCORPORATED
- Marek Hytha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making a semiconductor superlattices with different non-...
- Patent number 12,191,160
- Issue date Jan 7, 2025
- ATOMERA INCORPORATED
- Keith Doran Weeks
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making gate-all-around (GAA) device including a superlat...
- Patent number 12,142,641
- Issue date Nov 12, 2024
- ATOMERA INCORPORATED
- Keith Doran Weeks
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making semiconductor device including superlattice with...
- Patent number 12,119,380
- Issue date Oct 15, 2024
- ATOMERA INCORPORATED
- Keith Doran Weeks
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making semiconductor device including a superlattice and...
- Patent number 12,046,470
- Issue date Jul 23, 2024
- ATOMERA INCORPORATED
- Marek Hytha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around (GAA) device including a superlattice
- Patent number 11,978,771
- Issue date May 7, 2024
- ATOMERA INCORPORATED
- Keith Doran Weeks
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including a superlattice and enriched silicon...
- Patent number 11,923,418
- Issue date Mar 5, 2024
- ATOMERA INCORPORATED
- Marek Hytha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making semiconductor device including superlattice with...
- Patent number 11,848,356
- Issue date Dec 19, 2023
- ATOMERA INCORPORATED
- Keith Doran Weeks
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including superlattice with oxygen and carbon...
- Patent number 11,837,634
- Issue date Dec 5, 2023
- ATOMERA INCORPORATED
- Keith Doran Weeks
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making semiconductor device including a superlattice and...
- Patent number 11,810,784
- Issue date Nov 7, 2023
- ATOMERA INCORPORATED
- Marek Hytha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including superlattice with O18 enriched monol...
- Patent number 11,728,385
- Issue date Aug 15, 2023
- ATOMERA INCORPORATED
- Marek Hytha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making semiconductor device with selective etching of su...
- Patent number 11,721,546
- Issue date Aug 8, 2023
- ATOMERA INCORPORATED
- Marek Hytha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making semiconductor device including superlattice with...
- Patent number 11,682,712
- Issue date Jun 20, 2023
- ATOMERA INCORPORATED
- Marek Hytha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making semiconductor device with selective etching of su...
- Patent number 11,631,584
- Issue date Apr 18, 2023
- ATOMERA INCORPORATED
- Marek Hytha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making superlattice structures with reduced defect densi...
- Patent number 11,430,869
- Issue date Aug 30, 2022
- ATOMERA INCORPORATED
- Keith Doran Weeks
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor devices including hyper-abrupt junction region includ...
- Patent number 11,183,565
- Issue date Nov 23, 2021
- ATOMERA INCORPORATED
- Richard Burton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making semiconductor devices with hyper-abrupt junction...
- Patent number 10,937,868
- Issue date Mar 2, 2021
- ATOMERA INCORPORATED
- Richard Burton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making a varactor with a hyper-abrupt junction region in...
- Patent number 10,937,888
- Issue date Mar 2, 2021
- ATOMERA INCORPORATED
- Richard Burton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making a semiconductor device having a hyper-abrupt junc...
- Patent number 10,879,357
- Issue date Dec 29, 2020
- ATOMERA INCORPORATED
- Richard Burton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making a varactor with hyper-abrupt junction region incl...
- Patent number 10,868,120
- Issue date Dec 15, 2020
- ATOMERA INCORPORATED
- Richard Burton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making a FINFET including source and drain dopant diffus...
- Patent number 10,854,717
- Issue date Dec 1, 2020
- ATOMERA INCORPORATED
- Hideki Takeuchi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including body contact dopant diffusion blocki...
- Patent number 10,847,618
- Issue date Nov 24, 2020
- ATOMERA INCORPORATED
- Hideki Takeuchi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making semiconductor device including body contact dopan...
- Patent number 10,840,335
- Issue date Nov 17, 2020
- ATOMERA INCORPORATED
- Hideki Takeuchi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with metal-semiconductor contacts including ox...
- Patent number 10,840,336
- Issue date Nov 17, 2020
- ATOMERA INCORPORATED
- Daniel Connelly
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Varactor with hyper-abrupt junction region including a superlattice
- Patent number 10,840,388
- Issue date Nov 17, 2020
- ATOMERA INCORPORATED
- Richard Burton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making a FINFET having reduced contact resistance
- Patent number 10,840,337
- Issue date Nov 17, 2020
- ATOMERA INCORPORATED
- Hideki Takeuchi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor devices including hyper-abrupt junction region includ...
- Patent number 10,825,901
- Issue date Nov 3, 2020
- ATOMERA INCORPORATED
- Richard Burton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Varactor with hyper-abrupt junction region including spaced-apart s...
- Patent number 10,825,902
- Issue date Nov 3, 2020
- ATOMERA INCORPORATED
- Richard Burton
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR MAKING SEMICONDUCTOR DEVICES INCLUDING COMPOUND SEMICOND...
- Publication number 20250241018
- Publication date Jul 24, 2025
- ATOMERA INCORPORATED
- JERRY WAYNE JOHNSON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICES WITH GROUP III-N AND SILICON DEVICE REGIONS A...
- Publication number 20250241034
- Publication date Jul 24, 2025
- ATOMERA INCORPORATED
- JERRY WAYNE JOHNSON
Information Patent Application
SEMICONDUCTOR DEVICES INCLUDING COMPOUND SEMICONDUCTOR MATERIALS WI...
- Publication number 20250241035
- Publication date Jul 24, 2025
- ATOMERA INCORPORATED
- JERRY WAYNE JOHNSON
Information Patent Application
METHOD FOR MAKING SEMICONDUCTOR DEVICES INCLUDING COMPOUND SEMICOND...
- Publication number 20250239447
- Publication date Jul 24, 2025
- ATOMERA INCORPORATED
- JERRY WAYNE JOHNSON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MAKING SEMICONDUCTOR DEVICES WITH GROUP III-N AND SILICO...
- Publication number 20250239448
- Publication date Jul 24, 2025
- ATOMERA INCORPORATED
- JERRY WAYNE JOHNSON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PIEZOELECTRIC DEVICES INCLUDING COMPOUND SEMICONDUCTOR MATERIALS AN...
- Publication number 20250241033
- Publication date Jul 24, 2025
- ATOMERA INCORPORATED
- JERRY WAYNE JOHNSON
Information Patent Application
METHOD OF FABRICATING SEMICONDUCTOR DEVICES WITH ISOLATED SUPERLATT...
- Publication number 20250125149
- Publication date Apr 17, 2025
- ATOMERA INCORPORATED
- MAREK HYTHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MAKING A SEMICONDUCTOR DEVICE USING SUPERLATTICES WITH D...
- Publication number 20250105021
- Publication date Mar 27, 2025
- ATOMERA INCORPORATED
- KEITH DORAN WEEKS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING SUPERLATTICE WITH O18 ENRICHED MONOL...
- Publication number 20250107192
- Publication date Mar 27, 2025
- ATOMERA INCORPORATED
- Marek Hytha
Information Patent Application
METHOD FOR MAKING GATE-ALL-AROUND (GAA) DEVICE INCLUDING A SUPERLAT...
- Publication number 20250048701
- Publication date Feb 6, 2025
- ATOMERA INCORPORATED
- KEITH DORAN WEEKS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MAKING COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) DEVI...
- Publication number 20250048718
- Publication date Feb 6, 2025
- ATOMERA INCORPORATED
- DONGHUN KANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) DEVICES INCLUDING SUPE...
- Publication number 20250048729
- Publication date Feb 6, 2025
- ATOMERA INCORPORATED
- DONGHUN KANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MAKING SEMICONDUCTOR DEVICE INCLUDING SUPERLATTICE WITH...
- Publication number 20250006794
- Publication date Jan 2, 2025
- ATOMERA INCORPORATED
- KEITH DORAN WEEKS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MAKING SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND...
- Publication number 20240339319
- Publication date Oct 10, 2024
- ATOMERA INCORPORATED
- MAREK HYTHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND (GAA) DEVICE INCLUDING A SUPERLATTICE
- Publication number 20240194740
- Publication date Jun 13, 2024
- ATOMERA INCORPORATED
- KEITH DORAN WEEKS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH SELECTIVE ETCHING OF SU...
- Publication number 20240194482
- Publication date Jun 13, 2024
- ATOMERA INCORPORATED
- Marek Hytha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND ENRICHED SILICON...
- Publication number 20240170539
- Publication date May 23, 2024
- ATOMERA INCORPORATED
- MAREK HYTHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MAKING SEMICONDUCTOR DEVICE INCLUDING SUPERLATTICE WITH...
- Publication number 20240063268
- Publication date Feb 22, 2024
- ATOMERA INCORPORATED
- KEITH DORAN WEEKS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR MAKING SEMICONDUCTOR DEVICES WITH SUPERLATTICE AND EMBE...
- Publication number 20230411491
- Publication date Dec 21, 2023
- ATOMERA INCORPORATED
- MAREK HYTHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICES WITH EMBEDDED QUANTUM DOTS AND RELATED METHODS
- Publication number 20230411557
- Publication date Dec 21, 2023
- ATOMERA INCORPORATED
- MAREK HYTHA
- B82 - NANO-TECHNOLOGY
Information Patent Application
METHOD FOR MAKING SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND...
- Publication number 20230395374
- Publication date Dec 7, 2023
- ATOMERA INCORPORATED
- MAREK HYTHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING SUPERLATTICE WITH O18 ENRICHED MONOL...
- Publication number 20230361178
- Publication date Nov 9, 2023
- ATOMERA INCORPORATED
- Marek Hytha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH SELECTIVE ETCHING OF SU...
- Publication number 20230136797
- Publication date May 4, 2023
- ATOMERA INCORPORATED
- Marek Hytha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH SELECTIVE ETCHING OF SU...
- Publication number 20230135451
- Publication date May 4, 2023
- ATOMERA INCORPORATED
- Marek Hytha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND (GAA) DEVICE INCLUDING A SUPERLATTICE
- Publication number 20230121774
- Publication date Apr 20, 2023
- ATOMERA INCORPORATED
- KEITH DORAN WEEKS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MAKING GATE-ALL-AROUND (GAA) DEVICE INCLUDING A SUPERLAT...
- Publication number 20230122723
- Publication date Apr 20, 2023
- ATOMERA INCORPORATED
- KEITH DORAN WEEKS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING SUPERLATTICE WITH O18 ENRICHED MONOL...
- Publication number 20220384579
- Publication date Dec 1, 2022
- ATOMERA INCORPORATED
- Marek Hytha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MAKING SEMICONDUCTOR DEVICE INCLUDING SUPERLATTICE WITH...
- Publication number 20220384612
- Publication date Dec 1, 2022
- ATOMERA INCORPORATED
- Marek Hytha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND ENRICHED SILICON...
- Publication number 20220352322
- Publication date Nov 3, 2022
- ATOMERA INCORPORATED
- MAREK HYTHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MAKING SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND...
- Publication number 20220344155
- Publication date Oct 27, 2022
- ATOMERA INCORPORATED
- MAREK HYTHA
- H01 - BASIC ELECTRIC ELEMENTS

Marek Hytha

Person

Patents Grantslast 30 patents

Method for making semiconductor device including a superlattice and...

Method for making semiconductor device with selective etching of su...

Semiconductor device including superlattice with O18 enriched monol...

Method for making a semiconductor superlattices with different non-...

Method for making gate-all-around (GAA) device including a superlat...

Method for making semiconductor device including superlattice with...

Method for making semiconductor device including a superlattice and...

Gate-all-around (GAA) device including a superlattice

Semiconductor device including a superlattice and enriched silicon...

Method for making semiconductor device including superlattice with...

Semiconductor device including superlattice with oxygen and carbon...

Method for making semiconductor device including a superlattice and...

Semiconductor device including superlattice with O18 enriched monol...

Method for making semiconductor device with selective etching of su...

Method for making semiconductor device including superlattice with...

Method for making semiconductor device with selective etching of su...

Method for making superlattice structures with reduced defect densi...

Semiconductor devices including hyper-abrupt junction region includ...

Method for making semiconductor devices with hyper-abrupt junction...

Method for making a varactor with a hyper-abrupt junction region in...

Method for making a semiconductor device having a hyper-abrupt junc...

Method for making a varactor with hyper-abrupt junction region incl...

Method for making a FINFET including source and drain dopant diffus...

Semiconductor device including body contact dopant diffusion blocki...

Method for making semiconductor device including body contact dopan...

Semiconductor device with metal-semiconductor contacts including ox...

Varactor with hyper-abrupt junction region including a superlattice

Method for making a FINFET having reduced contact resistance

Semiconductor devices including hyper-abrupt junction region includ...

Varactor with hyper-abrupt junction region including spaced-apart s...

Patents Applicationslast 30 patents

METHOD FOR MAKING SEMICONDUCTOR DEVICES INCLUDING COMPOUND SEMICOND...

SEMICONDUCTOR DEVICES WITH GROUP III-N AND SILICON DEVICE REGIONS A...

SEMICONDUCTOR DEVICES INCLUDING COMPOUND SEMICONDUCTOR MATERIALS WI...

METHOD FOR MAKING SEMICONDUCTOR DEVICES INCLUDING COMPOUND SEMICOND...

METHOD FOR MAKING SEMICONDUCTOR DEVICES WITH GROUP III-N AND SILICO...

PIEZOELECTRIC DEVICES INCLUDING COMPOUND SEMICONDUCTOR MATERIALS AN...

METHOD OF FABRICATING SEMICONDUCTOR DEVICES WITH ISOLATED SUPERLATT...

METHOD FOR MAKING A SEMICONDUCTOR DEVICE USING SUPERLATTICES WITH D...

SEMICONDUCTOR DEVICE INCLUDING SUPERLATTICE WITH O18 ENRICHED MONOL...

METHOD FOR MAKING GATE-ALL-AROUND (GAA) DEVICE INCLUDING A SUPERLAT...

METHOD FOR MAKING COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) DEVI...

COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) DEVICES INCLUDING SUPE...

METHOD FOR MAKING SEMICONDUCTOR DEVICE INCLUDING SUPERLATTICE WITH...

METHOD FOR MAKING SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND...

GATE-ALL-AROUND (GAA) DEVICE INCLUDING A SUPERLATTICE

METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH SELECTIVE ETCHING OF SU...

SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND ENRICHED SILICON...

METHOD FOR MAKING SEMICONDUCTOR DEVICE INCLUDING SUPERLATTICE WITH...

METHODS FOR MAKING SEMICONDUCTOR DEVICES WITH SUPERLATTICE AND EMBE...

SEMICONDUCTOR DEVICES WITH EMBEDDED QUANTUM DOTS AND RELATED METHODS

METHOD FOR MAKING SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND...

SEMICONDUCTOR DEVICE INCLUDING SUPERLATTICE WITH O18 ENRICHED MONOL...

METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH SELECTIVE ETCHING OF SU...

METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH SELECTIVE ETCHING OF SU...

GATE-ALL-AROUND (GAA) DEVICE INCLUDING A SUPERLATTICE

METHOD FOR MAKING GATE-ALL-AROUND (GAA) DEVICE INCLUDING A SUPERLAT...

SEMICONDUCTOR DEVICE INCLUDING SUPERLATTICE WITH O18 ENRICHED MONOL...

METHOD FOR MAKING SEMICONDUCTOR DEVICE INCLUDING SUPERLATTICE WITH...

SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND ENRICHED SILICON...

METHOD FOR MAKING SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND...