Mark A. Gerber

Person

Plano, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor package with lead frame and recessed solder terminals
- Patent number 10,510,643
- Issue date Dec 17, 2019
- Texas Instruments Incorporated
- Mark Allen Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with lead frame and recessed solder terminals
- Patent number 9,978,667
- Issue date May 22, 2018
- Texas Instruments Incorporated
- Mark Allen Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packaged semiconductor devices
- Patent number 9,929,072
- Issue date Mar 27, 2018
- Texas Instruments Incorporated
- Mark A. Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and structure of packaging semiconductor devices
- Patent number 9,257,341
- Issue date Feb 9, 2016
- Texas Instruments Incorporated
- Mark A. Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit assembly
- Patent number 9,253,910
- Issue date Feb 2, 2016
- Texas Instruments Incorporated
- Mark Allen Gerber
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Semiconductor flip-chip system having oblong connectors and reduced...
- Patent number 9,129,955
- Issue date Sep 8, 2015
- Texas Instruments Incorporated
- Abram M. Castro
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating array-molded package-on-package
- Patent number 8,574,967
- Issue date Nov 5, 2013
- Texas Instruments Incorporated
- Mark A. Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for exposing and cleaning insulating coats from metal contac...
- Patent number 8,430,969
- Issue date Apr 30, 2013
- Texas Instruments Incorporated
- Mark A Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Array-molded package-on-package having redistribution lines
- Patent number 8,304,285
- Issue date Nov 6, 2012
- Texas Instruments Incorporated
- Mark A. Gerber
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Packaged system of semiconductor chips having a semiconductor inter...
- Patent number 8,133,761
- Issue date Mar 13, 2012
- Texas Instruments Incorporated
- Mark A. Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Array molded package-on-package having redistribution lines
- Patent number 7,944,034
- Issue date May 17, 2011
- Texas Instruments Incorporated
- Mark A. Gerber
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Method for fine-pitch, low stress flip-chip interconnect
- Patent number 7,790,509
- Issue date Sep 7, 2010
- Texas Instruments Incorporated
- Mark A Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Controlling flip-chip techniques for concurrent ball bonds in semic...
- Patent number 7,776,653
- Issue date Aug 17, 2010
- Texas Instruments Incorporated
- David N. Walter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package-on-package semiconductor assembly
- Patent number 7,675,152
- Issue date Mar 9, 2010
- Texas Instruments Incorporated
- Mark Allen Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Double density method for wirebond interconnect
- Patent number 7,655,552
- Issue date Feb 2, 2010
- Texas Instruments Incorporated
- Mark Allen Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertically integrated system-in-a-package
- Patent number 7,582,963
- Issue date Sep 1, 2009
- Texas Instruments Incorporated
- Mark A. Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Controlling flip-chip techniques for concurrent ball bonds in semic...
- Patent number 7,573,137
- Issue date Aug 11, 2009
- Texas Instruments Incorporated
- David N. Walter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packed system of semiconductor chips having a semiconductor interposer
- Patent number 7,573,139
- Issue date Aug 11, 2009
- Texas Instruments Incorporated
- Mark A. Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package-on-package system including integrated passiv...
- Patent number 7,569,918
- Issue date Aug 4, 2009
- Texas Instruments Incorporated
- Mark A. Gerber
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method for stacking semiconductor chips
- Patent number 7,547,630
- Issue date Jun 16, 2009
- Texas Instruments Incorporated
- Mark A. Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packaged system of semiconductor chips having a semiconductor inter...
- Patent number 7,390,700
- Issue date Jun 24, 2008
- Texas Instruments Incorporated
- Mark A. Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Double density method for wirebond interconnect
- Patent number 7,078,808
- Issue date Jul 18, 2006
- Texas Instruments Incorporated
- Mark Allen Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package device for use with multiple integrated circu...
- Patent number 6,916,682
- Issue date Jul 12, 2005
- FREESCALE SEMICONDUCTOR, INC.
- Mark A. Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-die semiconductor package
- Patent number 6,879,028
- Issue date Apr 12, 2005
- FREESCALE SEMICONDUCTOR, INC.
- Mark A. Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packaged semiconductor device and method of formation
- Patent number 6,858,932
- Issue date Feb 22, 2005
- FREESCALE SEMICONDUCTOR, INC.
- Mark A. Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low profile semiconductor device having improved heat dissipation
- Patent number 6,847,102
- Issue date Jan 25, 2005
- FREESCALE SEMICONDUCTOR, INC.
- Mark A. Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packaged semiconductor with multiple rows of bond pads and method t...
- Patent number 6,476,506
- Issue date Nov 5, 2002
- Motorola, Inc.
- Shawn M. O'Connor
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-chip assembly having a heat sink and method thereof
- Patent number 6,130,821
- Issue date Oct 10, 2000
- Motorola, Inc.
- Mark Allen Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Replaceable power module
- Patent number 6,020,634
- Issue date Feb 1, 2000
- Dallas Semiconductor Corporation
- Mark A. Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power cap
- Patent number 5,892,304
- Issue date Apr 6, 1999
- Dallas Semiconductor
- Neil McLellan
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR PACKAGE WITH LEAD FRAME AND RECESSED SOLDER TERMINALS
- Publication number 20180261531
- Publication date Sep 13, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Mark Allen Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL SIDED EMBEDDED DIE AND FABRICATION OF SAME BACKGROUND
- Publication number 20160240392
- Publication date Aug 18, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Anindya Poddar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGED SEMICONDUCTOR DEVICES
- Publication number 20160111349
- Publication date Apr 21, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Mark A. Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE HAVING NON-CIRCULAR CONNECTORS
- Publication number 20150371963
- Publication date Dec 24, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Abram M. Castro
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL SIDED EMBEDDED DIE AND FABRICATION OF SAME BACKGROUND
- Publication number 20150147845
- Publication date May 28, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Anindya Poddar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE HAVING RECESSED SOLDER TERMINALS
- Publication number 20150041994
- Publication date Feb 12, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Mark Allen Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and Structure of Packaging Semiconductor Devices
- Publication number 20150008583
- Publication date Jan 8, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Mark A. Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND STRUCTURE OF PANELIZED PACKAGING OF SEMICONDUCTOR DEVICES
- Publication number 20150008566
- Publication date Jan 8, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Mark A. Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DISCRETE COMPONENT ASSEMBLY
- Publication number 20140211444
- Publication date Jul 31, 2014
- Mark Allen Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CIRCUIT ASSEMBLY
- Publication number 20140211439
- Publication date Jul 31, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Mark Allen Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Fabricating Array-Molded Package-on-Package
- Publication number 20140030851
- Publication date Jan 30, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Mark A. Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Fabricating Array-Molded Package-on-Package
- Publication number 20130189814
- Publication date Jul 25, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Mark A. Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Array-Molded Package-On-Package Having Redistribution Lines
- Publication number 20110183465
- Publication date Jul 28, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Mark A. GERBER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Fabricating Array-Molded Package-on-Package
- Publication number 20110165731
- Publication date Jul 7, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Mark A. Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Cleaning Insulating Coats from Metal Contact Surfaces
- Publication number 20110011424
- Publication date Jan 20, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Mark Allen GERBER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Flip-Chip System Having Oblong Connectors and Reduced...
- Publication number 20100193944
- Publication date Aug 5, 2010
- Texas Instrument Incorporated
- Abram M. CASTRO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Chip Package System Vertical Interconnect
- Publication number 20100084755
- Publication date Apr 8, 2010
- Mark Allen Gerber
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
FINE-PITCH OBLONG SOLDER CONNECTIONS FOR STACKING MULTI-CHIP PACKAGES
- Publication number 20100072600
- Publication date Mar 25, 2010
- Texas Instrument Incorporated
- Mark A. GERBER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FINE-PITCH, LOW STRESS FLIP-CHIP INTERCONNECT
- Publication number 20090325348
- Publication date Dec 31, 2009
- TEXAS INSTRUMENTS INCORPORATED
- MARK A. GERBER
- C09 - DYES PAINTS POLISHES NATURAL RESINS ADHESIVES MISCELLANEOUS COMPOSITION...
Information Patent Application
Package on Package Structure with thin film Interposing Layer
- Publication number 20090309236
- Publication date Dec 17, 2009
- Mark Allen Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Controlling Flip-Chip Techniques for Concurrent Ball Bonds in Semic...
- Publication number 20090269883
- Publication date Oct 29, 2009
- TEXAS INSTRUMENTS INCORPORATED
- David N. Walter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Packaged System of Semiconductor Chips Having a Semiconductor Inter...
- Publication number 20090258459
- Publication date Oct 15, 2009
- TEXAS INSTRUMENTS INCORPORATED
- MARK A. GERBER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGED INTEGRATED CIRCUITS HAVING SURFACE MOUNT DEVICES AND METHO...
- Publication number 20090166889
- Publication date Jul 2, 2009
- Rajen Murugan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE HAVING THROUGH-SILICON VIAS FOR HIGH CURRENT,H...
- Publication number 20090115026
- Publication date May 7, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Mark Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Stacking Semiconductor Chips
- Publication number 20090079067
- Publication date Mar 26, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Mark A. Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Package-on-Package System Including Integrated Passiv...
- Publication number 20080315387
- Publication date Dec 25, 2008
- TEXAS INSTRUMENTS INCORPORATED
- MARK A. GERBER
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Array molded package-on-package having redistribution lines
- Publication number 20080315385
- Publication date Dec 25, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Mark A. Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Fabricating Array-Molded Package-On-Package
- Publication number 20080284045
- Publication date Nov 20, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Mark A. Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High Input/Output, Low Profile Package-On-Package Semiconductor System
- Publication number 20080258286
- Publication date Oct 23, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Mark A. Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Packed System of Semiconductor Chips Having a Semiconductor Interposer
- Publication number 20080246138
- Publication date Oct 9, 2008
- TEXAS INSTRUMENTS INCORPORATED
- MARK A. GERBER
- H01 - BASIC ELECTRIC ELEMENTS

Mark A. Gerber

Person

Patents Grantslast 30 patents

Semiconductor package with lead frame and recessed solder terminals

Semiconductor package with lead frame and recessed solder terminals

Packaged semiconductor devices

Method and structure of packaging semiconductor devices

Circuit assembly

Semiconductor flip-chip system having oblong connectors and reduced...

Method for fabricating array-molded package-on-package

Method for exposing and cleaning insulating coats from metal contac...

Array-molded package-on-package having redistribution lines

Packaged system of semiconductor chips having a semiconductor inter...

Array molded package-on-package having redistribution lines

Method for fine-pitch, low stress flip-chip interconnect

Controlling flip-chip techniques for concurrent ball bonds in semic...

Package-on-package semiconductor assembly

Double density method for wirebond interconnect

Vertically integrated system-in-a-package

Controlling flip-chip techniques for concurrent ball bonds in semic...

Packed system of semiconductor chips having a semiconductor interposer

Semiconductor package-on-package system including integrated passiv...

Method for stacking semiconductor chips

Packaged system of semiconductor chips having a semiconductor inter...

Double density method for wirebond interconnect

Semiconductor package device for use with multiple integrated circu...

Multi-die semiconductor package

Packaged semiconductor device and method of formation

Low profile semiconductor device having improved heat dissipation

Packaged semiconductor with multiple rows of bond pads and method t...

Multi-chip assembly having a heat sink and method thereof

Replaceable power module

Power cap

Patents Applicationslast 30 patents

SEMICONDUCTOR PACKAGE WITH LEAD FRAME AND RECESSED SOLDER TERMINALS

DUAL SIDED EMBEDDED DIE AND FABRICATION OF SAME BACKGROUND

PACKAGED SEMICONDUCTOR DEVICES

SEMICONDUCTOR DEVICE HAVING NON-CIRCULAR CONNECTORS

DUAL SIDED EMBEDDED DIE AND FABRICATION OF SAME BACKGROUND

SEMICONDUCTOR PACKAGE HAVING RECESSED SOLDER TERMINALS

Method and Structure of Packaging Semiconductor Devices

METHOD AND STRUCTURE OF PANELIZED PACKAGING OF SEMICONDUCTOR DEVICES

DISCRETE COMPONENT ASSEMBLY

CIRCUIT ASSEMBLY

Method for Fabricating Array-Molded Package-on-Package

Method for Fabricating Array-Molded Package-on-Package

Array-Molded Package-On-Package Having Redistribution Lines

Method for Fabricating Array-Molded Package-on-Package

Method for Cleaning Insulating Coats from Metal Contact Surfaces

Semiconductor Flip-Chip System Having Oblong Connectors and Reduced...

Semiconductor Chip Package System Vertical Interconnect

FINE-PITCH OBLONG SOLDER CONNECTIONS FOR STACKING MULTI-CHIP PACKAGES

METHOD FOR FINE-PITCH, LOW STRESS FLIP-CHIP INTERCONNECT

Package on Package Structure with thin film Interposing Layer

Controlling Flip-Chip Techniques for Concurrent Ball Bonds in Semic...

Packaged System of Semiconductor Chips Having a Semiconductor Inter...

PACKAGED INTEGRATED CIRCUITS HAVING SURFACE MOUNT DEVICES AND METHO...

SEMICONDUCTOR DEVICE HAVING THROUGH-SILICON VIAS FOR HIGH CURRENT,H...

Method for Stacking Semiconductor Chips

Semiconductor Package-on-Package System Including Integrated Passiv...

Array molded package-on-package having redistribution lines

Method for Fabricating Array-Molded Package-On-Package

High Input/Output, Low Profile Package-On-Package Semiconductor System

Packed System of Semiconductor Chips Having a Semiconductor Interposer