Patent Application
20100084755
The invention relates to electronic semiconductor chips, their packaging, and manufacturing. More particularly, the invention relates to microelectronic semiconductor systems having vertically stacked and interconnected semiconductor chips contained within a single package and to methods related to the manufacture of such package systems.
There is generally an ongoing need to minimize the size of electronic apparatus. At the same time, the demand for increased features results in an increase in the number of components on a given chip. Efforts are continuously being made to design and manufacture chips and packages with reduced area, but attempts to increase density while reducing area eventually reach a practical limit. As designers attempt to maximize the use of substrate, semiconductor chip, and system area, vertical stacking of system components becomes increasingly attractive.
Packaged semiconductor chip systems containing two or more stacked semiconductor chips typically include a first semiconductor chip, such as an IC (integrated circuit), with bond pads disposed on one of its surfaces. A second semiconductor chip is affixed to the exposed surface of the first chip. One or more additional semiconductor chips may also in turn be stacked in a similar manner to form a multi-layer, multi-chip package system containing two, three or more stacked semiconductor chips operably coupled to one another, either directly, or through a package substrate, possibly for external connection elsewhere. The stacked semiconductor chips may include various components such as ICs, substrate layers, and spacers, for example. Encapsulant is typically applied to cover the stacked semiconductor chips, any associated bondwires, and at least a portion of the package substrate. Surface-mountable semiconductor chips used in stack systems generally have their corresponding surface contacts coupled using solder balls to form the desired electrical connections.
Although electrically connected, the semiconductor chip stacks in some package systems known in the art lack the mechanical strength required for withstanding stresses encountered in common operating environments. In efforts to address this problem, dielectric underfill material is usually interposed between the chips in such a stack in order to provide added mechanical strength and increased durability, as well as to protect the contacts from external hazards. Underfilling introduces further challenges to the assembly process, such as necessitating additional assembly steps, which typically equates to increased costs. Underfilling sometimes fails to prevent reliability problems, often due to the formation of voids or inadequate or uneven distribution of the underfill material. Generally, as package size decreases, underfilling becomes more problematic, particularly for “low profile” stacks in which low die-to-die standoff heights constrain underfilling, making the need for alternative strengthening structures become more pronounced.
Due to these and other technical challenges, improved vertically stacked semiconductor chip package systems with mechanical interconnects with reduced dependence on the use of underfill for strength, and improved mechanical connections among stack layers, and related methods for their manufacture, would be useful and advantageous in the arts. The present invention is directed to overcoming, or at least reducing the effects of one or more of the problems existing in the art.
In carrying out the principles of the present invention, in accordance with preferred embodiments thereof, the invention provides vertically interconnected semiconductor package systems and methods for their manufacture. The invention provides systems and methods by which multiple semiconductor chips may be vertically stacked and joined with reliable, planar, mechanically strong interconnections with improved strength, and reduced reliance on underfill for mechanical strength. One approach sometimes used in an effort to strengthen mechanical bonds between stacked chips is the use of anchor pads made from solder. The Applicants have identified a problem with this approach, in that when the solder becomes liquid during reflow, it tends to form a cohesive mass, or “ball”, the size of which is largely dependent upon the amount of solder present. In general, larger, thicker, balls form on larger pads, such as anchor pads, and smaller, thinner, balls tend to form on smaller pads, such as electrical contacts. As a result, efforts to use enlarged anchor pads to strengthen mechanical bonds between chips in a stack are hampered by the non-planarity that results from differences in solder heights, causing misalignment and/or insufficient strength of joints between adjacent surfaces in a stack. Additionally, stacks in which the layers are connected using anchor pads may require underfilling not only for sealing, but for mechanical strength as well.
The Applicants, after much study, experimentation, and application of experience and skill, have identified shortcomings in the extant art and have developed inventive solutions for avoiding and correcting problems found in the prior art by employing fusible metallic coupling elements for mechanical connections, rather than traditional solder. The invention provides devices, systems, and methods by which multiple semiconductor chips may be vertically stacked and joined with reliable planar mechanical interconnections with reduced dependence on underfilling for strength.
According to one aspect of the invention, methods for assembling a stacked semiconductor package system include steps for providing at least one fusible metallic coupling element at the periphery of a surface of a first semiconductor chip. Like fusible metallic coupling elements are provided at the periphery of a second semiconductor chip. The chip surfaces, and corresponding fusible metallic coupling elements, are then brought together, heated, and at least one eutectic alloy fused metallic mechanical coupling is formed at the junction between the adjoining semiconductor chip surfaces.
According to another aspect of the invention, preferred embodiments provide a gold-tin eutectic alloy fused metallic mechanical coupling including, by weight, about eighty percent gold and about twenty percent tin.
According to another aspect of the invention, a preferred embodiment of a method for assembling a stacked semiconductor chip package includes steps for providing fusible metallic coupling elements configured for mechanically interfacing prior to heating to form a fused metallic mechanical coupling.
According to another aspect of the invention, a preferred method includes steps of providing gold, tin, or alloy-plated fusible metallic coupling elements for heating in order to form fused metallic mechanical couplings.
According to yet another aspect of the invention, the methods of the invention may be used for forming fused metallic couplings between interconnecting semiconductor chip surfaces in systems of three or more vertically stacked semiconductor chips.
According to still another aspect of the invention, an exemplary embodiment of a stacked semiconductor chip package system has a first semiconductor chip with a surface bearing at least one first fusible metallic mechanical coupling. A second semiconductor chip also has a surface bearing at least one second fusible metallic mechanical coupling element corresponding with a first fusible metallic mechanical coupling element of the first semiconductor chip. The corresponding first and second fusible metallic mechanical coupling elements are fused, forming one or more gold-tin eutectic alloy fused metallic couplings for mechanically bonding the semiconductor chips together.
According to another aspect of the invention, a preferred embodiment of a semiconductor chip package system includes a fused metallic coupling ring mechanically bonding stacked semiconductor chips together.
According to another aspect of the invention, a preferred embodiment of a semiconductor chip package system includes fused metallic couplings in the form of anchor posts mechanically bonding stacked semiconductor chips together at each corner.
The invention has advantages including but not limited to providing mechanically strong semiconductor chip interconnections in stacked semiconductor chip package systems, and reducing costs associated with stacked semiconductor chip package system assembly. In some applications, mechanical couplings may be made in steps independent from those used for the formation of electrical connections. These and other features, advantages, and benefits of the present invention can be understood by one of ordinary skill in the arts upon careful consideration of the detailed description of representative embodiments of the invention in connection with the accompanying drawings.
The present invention will be more clearly understood from consideration of the following detailed description and drawings in which:
References in the detailed description correspond to like references in the various drawings unless otherwise noted. Descriptive and directional terms used in the written description such as first, second, top, bottom, side, etc., refer to the drawings themselves as laid out on the paper and not to physical limitations of the invention unless specifically noted. The drawings are not to scale, and some features of embodiments shown and discussed are simplified or amplified for illustrating the principles, features, and advantages of the invention.
The invention provides systems and related methods for mechanically interconnecting vertically stacked semiconductor chips in a single package. Examples of preferred embodiments include alternative implementations illustrating and describing improved semiconductor chip stack system interconnections. The term semiconductor chips used herein with reference to the invention, is broadly defined to include stack components suitable for joining using metallurgical joints, and may consist of ICs, PCBs, PWBs, or other components made from semiconductor materials such as silicon, germanium, gallium-arsenide, silicon-carbide, indium-nitride, or other combinations.
Referring to the drawings,
Further understanding of the invention may be gained by referring to the additional figures provided.
In
The invention preferably uses gold-tin eutectic alloy selected for relatively low-temperature processing. In some embodiments, the first and second fusible metallic coupling elements may provide distinct optical profiles, which may be aligned using optical sensor equipment. Cutaway macro side views of steps used in the formation of a fused metallic coupling 28 are depicted in
As portrayed by the transition from
Avoiding or reducing problems associated with the reflow of liquid solder, the fused metallic couplings are preferably formed using metals selected for the formation of eutectic alloys at relatively low temperatures. A eutectic alloy has the property of having a precise temperature point at which all components of the alloy solidify at a single temperature. It should be appreciated that, in contrast, a non-eutectic alloy has a plastic melting range, and that component metals of the alloy solidify at different temperatures. Another property of eutectic alloys is that they have a subsequent melting point higher than that required for their formation. In the presently most preferred embodiment, a gold-tin eutectic alloy proportioned approximately 80-20 percent by weight is used. In this example, the eutectic alloy formed using a mixture of 80-20 gold-tin joins the stacked metallic coupling elements using relatively low-temperature heating. Using a mixture of 80-20 (by weight) gold-tin, the eutectic point is about 278° C. Thus, using suitably prepared fusible metallic couplings, a fused metallic coupling is formed of gold-tin eutectic alloy when the contacting surfaces are heated to 278° C. After the eutectic alloy is allowed to cool to equilibrium, due to the properties of the eutectic alloy of gold and tin, the fused metallic coupling subsequently has a melting point significantly higher than that required for its formation. The significantly higher melting point of the fused metallic coupling ensures that it will not liquefy during subsequent heating used for completing the stacked package assembly, such as may be used for standard solder reflow processes, which typically exceed 300° C. Thus, the fused metallic couplings described may advantageously be used to secure layers in a stacked package, forming solid mechanical joints capable of withstanding subsequent solder reflow steps when required. Since the fused metallic couplings do not become liquid during subsequent heating such as for common soldering operations, i.e., up to about 300° C., uniform height established between the adjoining surfaces during the formation of the fused metallic couplings can be maintained irrespective of subsequent soldering reflow steps.
The possible variations within the scope of the invention are numerous and cannot all be shown. Optionally, when fused metallic couplings are formed using gold-tin eutectic alloy, electrical interconnects among the chips may be made as well. Using the invention provides additional advantages in obtaining uniform planarity among mechanical connections 28 and electrical connections 30, which may be formed by fusing aligned contacts 30 on the facing chips 12, 26. Again referring to the example shown in
An alternative view showing the assembly of fused metallic couplings is shown in
It should be understood that the stacked semiconductor chip package system 10 of the invention may be used in vertical stack configurations of more than two semiconductor chips. For example, referring to
The methods and systems of the invention provide one or more advantages including but not limited to reducing the planar area occupied by reliable vertically stacked semiconductor chip package systems, improving strength characteristics, and reducing the mechanical strength demanded of underfill material and electrical bonds. While the invention has been described with reference to certain illustrative embodiments, those described herein are not intended to be construed in a limiting sense. For example, variations or combinations of steps or materials in the embodiments shown and described may be used in particular cases without departure from the invention. Particularly with respect to the number of semiconductor chip interconnections in a stack, as well as size, material, geometry, and number of fused metallic couplings, various modifications and combinations of the illustrative embodiments as well as other advantages and embodiments of the invention will be apparent to persons skilled in the arts upon reference to the drawings, description, and claims.
