The invention relates to electronic semiconductor chips and manufacturing. More particularly, the invention relates to systems and associated methods for manufacturing vertically stacked semiconductor device assemblies with improved interposing layers between semiconductor device layers.
There is generally an ongoing need to minimize the size of electronic apparatus. At the same time, the demand for increased features results in an increase in the number of components on a given device. Efforts are continuously being made to design and manufacture devices and packages with reduced area, but attempts to increase density while reducing area eventually reach a practical limit. As designers attempt to maximize the use of substrate, semiconductor device, and system area, vertical stacking of system components becomes increasingly attractive.
In order to reduce or eliminate some of the problems associated with wirebonding and to reduce the footprint of a completed assembly, surface-mountable, or flip-chip, semiconductor devices are sometimes preferred for vertically stacked applications. Generally, semiconductor devices are stacked in such assemblies by mounting the back side of a semiconductor device to an insulating substrate, with exposed surface contacts designed to accept electrical coupling to corresponding surface contacts. In such assemblies, the connection between two semiconductor devices is generally accomplished using an interposing layer made from rigid material, such as an organic substrate, provided with the requisite electrical connections, generally solder balls. One or more additional semiconductor devices may also in turn be stacked in a similar manner to form a multi-layer, multi-device package system containing two, three or more stacked semiconductor devices operably coupled to one another, usually through the package substrate, and usually including provision for external connection elsewhere.
Problems remain in the present state of the art, however. The desirability of reducing the footprint of the assembly, and thus the footprint of each respective layer, is beset with challenges including pitch and layout limitations inherent in forming the interposing layer using a rigid substrate material. The expense of fashioning such an interposing layer is prohibitive in some instances, particularly in applications where fine pitch microbump interconnections are desired. In applications where interlayer vertical connections are desired, efforts to use through-silicon vias in the interposing layer substrate are beset with manufacturing difficulties that rapidly increase the expense of manufacturing as the available area decreases. It is of course desirable to make the interposing layer only as thick as absolutely necessary in order to help minimize the overall height of the assembly. Unfortunately, with the substrate materials used in the arts, a certain minimum thickness is required in order to provide the interposing layer with sufficient mechanical strength to withstand manufacturing and handling operations, and to resist warping. Warping of the overall assembly can be an additional problem, particularly in cases where stack layers of varying areas are used, resulting in overhangs susceptible to warpage. Other considerations, which can lead to further complications, include the need to keep electrical connections short to optimize speed, and to provide design flexibility for addressing layout and timing concerns.
Due to these and other technological problems, improved vertically stacked semiconductor device assemblies and methods for their manufacture would be useful and advantageous contributions to the art. The present invention is directed to overcoming, or at least reducing, problems present in the prior art, and contributes one or more heretofore unforeseen advantages indicated herein.
In carrying out the principles of the present invention, in accordance with preferred embodiments thereof, the invention provides novel and useful improvements for vertically stacked semiconductor device assemblies. Through diligent study, experimentation, and analysis, the inventor has determined that thin film interposing layers may be used in order to overcome some of the problems with traditional rigid interposing layers known in the arts. Endeavors to use thin film interposers for vertically coupling layers of semiconductor stack assemblies, in order to reduce the thickness of the assemblies, have led to synergistic innovations in using thin film based interposers to realize further advantages such as increased electrical connection density, improved layout flexibility, reduced manufacturing costs, and in some cases increased mechanical strength and durability. Using the invention, the interposing layer may be provided with a full array of fine pitch of electrical contact pads. Advantages also accrue when contact pads are called for on the periphery only, as they may be provided at a higher density than previously known in the art. Aspects of the invention are directed to making vertical interconnections among layers in a stack assembly without the need for using potentially more complex and expensive through-silicon via technology, increasing design flexibility and reducing manufacturing costs.
According to one aspect of the invention, in an example of a preferred embodiment, a semiconductor device assembly using the invention includes a base substrate having a region for mounting a device and adjacent electrical contacts on its surface. A first semiconductor device has one surface affixed to the device mounting region, and numerous electrical contacts on its opposite surface. An interposing layer is affixed thereto, and the contacts of the first device are electrically connected to suitable contacts on the interposing layer. The interposing layer is made from a thin insulating film or tape material endowed with numerous electrical contacts on its surfaces. A second semiconductor device is likewise attached and electrically connected to the other surface of the interposing layer. The interposing layer also includes a number of electrical contacts suitable for electrically coupling directly with the electrical contacts on the base substrate.
According to another aspect of the invention, in preferred embodiments, the electrical contacts on the interposing layer for electrically coupling directly with the electrical contacts on the base substrate comprise metal studs, wirebond pins, or solder-coated copper inserts.
According to another aspect of the invention, in a vertically stacked semiconductor device assembly incorporating an interposing layer as described, in a preferred embodiment, a third semiconductor device is affixed to the second semiconductor device, having electrical contacts configured for operably coupling directly to electrical contacts on the base substrate.
According to another aspect of the invention, in an example of a preferred embodiment, a semiconductor device assembly includes electrical contacts on a second surface of the interposing layer configured for operably coupling directly to electrical contacts on the third semiconductor device.
According to still another aspect of the invention, an interposing layer for use between stacked devices in a stacked semiconductor device assembly includes a thin insulating film or tape supporting a plurality of electrical contacts on each of its surfaces for coupling with contacts on adjacent semiconductor device layers of the stack. On at least one of the interposing layer surfaces, electrical contacts configured for operably coupling directly to contacts on a non-adjacent layer of the stack are also included.
According to yet another aspect of the invention, in preferred embodiments, the electrical contacts on the interposing layer for electrically coupling directly with electrical contacts on a non-adjacent layer of the stack are made using for example, metal studs, wirebond studs, or solder-coated copper.
The invention has advantages including but not limited to one or more of the following: decreased footprint in package on package structures; decreased interposing layer thickness; increased versatility in assembly component selection; improved interlayer connections; reduced warpage; and reduced cost. These and other features, advantages, and benefits of the present invention can be understood by one of ordinary skill in the arts upon careful consideration of the detailed description of representative embodiments of the invention in connection with the accompanying drawings.
The present invention will be more clearly understood from consideration of the following detailed description and drawings in which:
The drawings are not to scale, and some features of embodiments shown and discussed are simplified or amplified for illustrating principles and features, as well as anticipated and unanticipated advantages of the invention.
While the making and using of various exemplary embodiments of the invention are discussed herein, it should be appreciated that the present invention provides inventive concepts which can be embodied in a wide variety of specific contexts. It should be understood that the invention may be practiced with vertically stacked semiconductor package on package assemblies and associated manufacturing processes of various types and materials without altering the principles of the invention. For purposes of clarity, detailed descriptions of functions and systems familiar to those skilled in the semiconductor device, packaging, and manufacturing arts are not included.
In general, the invention provides vertically stacked semiconductor device assemblies using thin film or tape interposing layers structured for vertically coupling layers of the stack. Features of the invention are advantageous in terms of increased electrical connection density, decreased assembly footprint, decreased assembly thickness, and even increased mechanical strength and durability due to improved vertical connections among stack components.
Referring initially to
As shown and described, the interposing layer 26 used in implementing the invention is preferably made from a foundation 30 of polyimide film or similar material. Such film, or tape, is preferred generally for its insulating properties, temperature resistance, strength, flexibility, chemical and electrical properties, and thinness relative to more rigid alternative materials. Thicknesses ranging from about 1 to 10 mil are available in the arts and may be used, with the thinner films typically preferred for the implementation of the invention. The surface contacts, e.g., 32, 34, on the interposing layer 26 are preferably surface-mount contacts of various configurations known in the arts, typically exposed copper, gold, or suitable conductive alloy microbumps or bond pads. The metal studs 46 are preferably formed from suitable metals, such as gold, copper, or alloy, using common metallurgical bonding techniques for the formation of single studs, or pins, as shown 46, for making operable electrical connections directly to contacts on a non-adjacent layer, e.g. 12, of the assembly 10. It should also be appreciated by those skilled in the arts, that solder balls or double pins (not shown) may also be used in some applications. The use of thin film 30 for the interposing layer 26 permits the use of finer pitch surface contacts, e.g. 22, 32, 34, as well as a thinner interposing layer 26, ultimately resulting in a thinner stacked package assembly 10. Using the thin-film structure, a finer pitch may be used between the metal studs 46 than with alternatives known in the arts. Another unexpected advantage of the invention, due to the mechanical properties provided by having more numerous vertical studs, solder balls or pins among stack layers, is increased rigidity in some applications, providing package on package assemblies with increased resistance to warpage. Encapsulant and/or underfill material (not shown) may also be used to mechanically bond stack components as known in the arts.
Now referring primarily to
The possible variations of implementations of the invention are many and cannot, and need not, all be shown. An additional example of a preferred embodiment is provided in
An additional alternative embodiment of the invention is shown in
The methods and systems of the invention provide one or more advantages including but not limited to surprisingly effective reduction of warpage in stacked packages, increased pitch, reduced footprint, reduced thickness, increased speed, increased design flexibility in assembly configuration, and reduced costs. While the invention has been described with reference to certain illustrative embodiments, those described herein are not intended to be construed in a limiting sense. For example, variations or combinations of steps or materials in the embodiments shown and described may be used in particular cases without departure from the invention. Various modifications and combinations of the illustrative embodiments as well as other advantages and embodiments of the invention will be apparent to persons skilled in the arts upon reference to the drawings, description, and claims.