Mark Leinwander

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Autonomous memory architecture
- Patent number 11,586,577
- Issue date Feb 21, 2023
- Micron Technology, Inc.
- Sean Eilert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
XOR parity management on a physically addressable solid state drive
- Patent number 10,776,200
- Issue date Sep 15, 2020
- Intel Corporation
- Jeffrey McVay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Autonomous memory architecture
- Patent number 10,769,097
- Issue date Sep 8, 2020
- Micron Technologies, Inc.
- Sean Eilert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device for a hierarchical memory architecture
- Patent number 10,725,956
- Issue date Jul 28, 2020
- Micron Technology, Inc.
- Sean Eilert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using out-of-band signaling to communicate with daisy chained nonvo...
- Patent number 10,388,330
- Issue date Aug 20, 2019
- Micron Technology, Inc.
- Mark Leinwander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device for a hierarchical memory architecture
- Patent number 10,031,879
- Issue date Jul 24, 2018
- Micron Technology, Inc.
- Sean Eilert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Autonomous memory architecture
- Patent number 9,779,057
- Issue date Oct 3, 2017
- Micron Technology, Inc.
- Sean Eilert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using out-of-band signaling to communicate with daisy chained nonvo...
- Patent number 9,741,398
- Issue date Aug 22, 2017
- Micron Technology, Inc.
- Mark Leinwander
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device for a hierarchical memory architecture
- Patent number 9,626,327
- Issue date Apr 18, 2017
- Micron Technology, Inc.
- Sean Eilert
- G11 - INFORMATION STORAGE
Information Patent Grant
Autonomous memory subsystem architecture
- Patent number 9,612,750
- Issue date Apr 4, 2017
- Micron Technologies, Inc.
- Sean Eilert
- G11 - INFORMATION STORAGE
Information Patent Grant
Switchable on-die memory error correcting engine
- Patent number 9,239,759
- Issue date Jan 19, 2016
- Micron Technology, Inc.
- Gurkirat Billing
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device for a hierarchical memory architecture
- Patent number 9,123,409
- Issue date Sep 1, 2015
- Micron Technology, Inc.
- Sean Eilert
- G11 - INFORMATION STORAGE
Information Patent Grant
Block-based storage device with a memory-mapped interface
- Patent number 9,116,800
- Issue date Aug 25, 2015
- Micron Technology, Inc.
- Samuel Post
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Autonomous memory subsystem architecture
- Patent number 9,015,440
- Issue date Apr 21, 2015
- Micron Technology, Inc.
- Sean Eilert
- G11 - INFORMATION STORAGE
Information Patent Grant
Block-based storage device with a memory-mapped interface
- Patent number 8,898,417
- Issue date Nov 25, 2014
- Micron Technology, Inc.
- Sam Post
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Switchable on-die memory error correcting engine
- Patent number 8,793,554
- Issue date Jul 29, 2014
- Micron Technology, Inc.
- Gurkirat Billing
- G11 - INFORMATION STORAGE
Information Patent Grant
Switchable on-die memory error correcting engine
- Patent number 8,495,467
- Issue date Jul 23, 2013
- Micron Technology, Inc.
- Gurkirat Billing
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory to store memory remap information
- Patent number 8,412,987
- Issue date Apr 2, 2013
- Micron Technology, Inc.
- Gurkirat Billing
- G11 - INFORMATION STORAGE
Information Patent Grant
Selecting an integrated circuit from different integrated circuit a...
- Patent number 5,867,721
- Issue date Feb 2, 1999
- Intel Corporation
- Mark P. Leinwander
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
AUTONOMOUS MEMORY ARCHITECTURE
- Publication number 20200401550
- Publication date Dec 24, 2020
- Micron Technology Inc.
- Sean Eilert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE FOR A HIERARCHICAL MEMORY ARCHITECTURE
- Publication number 20180322085
- Publication date Nov 8, 2018
- Micron Technology, Inc.
- Sean Eilert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTONOMOUS MEMORY ARCHITECTURE
- Publication number 20180024966
- Publication date Jan 25, 2018
- Micron Technology, Inc.
- Sean Eilert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE FOR A HIERARCHICAL MEMORY ARCHITECTURE
- Publication number 20170220516
- Publication date Aug 3, 2017
- Micron Technology, Inc.
- Sean Eilert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE FOR A HIERARCHICAL MEMORY ARCHITECTURE
- Publication number 20150370750
- Publication date Dec 24, 2015
- Micron Technology, Inc.
- Sean Eilert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTONOMOUS MEMORY SUBSYSTEM ARCHITECTURE
- Publication number 20150205530
- Publication date Jul 23, 2015
- Micron Technology, Inc.
- Sean Eilert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BLOCK-BASED STORAGE DEVICE WITH A MEMORY-MAPPED INTERFACE
- Publication number 20150081998
- Publication date Mar 19, 2015
- Micron Technology, Inc.
- Samuel Post
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SWITCHABLE ON-DIE MEMORY ERROR CORRECTING ENGINE
- Publication number 20140337688
- Publication date Nov 13, 2014
- Gurkirat Billing
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SWITCHABLE ON-DIE MEMORY ERROR CORRECTING ENGINE
- Publication number 20130305123
- Publication date Nov 14, 2013
- Micron Technology, Inc.
- Gurkirat Billing
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Nonvolatile Storage with Disparate Memory Types
- Publication number 20110167197
- Publication date Jul 7, 2011
- Mark Leinwander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTONOMOUS MEMORY ARCHITECTURE
- Publication number 20110067039
- Publication date Mar 17, 2011
- Sean Eilert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTONOMOUS SUBSYSTEM ARCHITECTURE
- Publication number 20110066796
- Publication date Mar 17, 2011
- Sean Eilert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-VOLATILE MEMORY TO STORE MEMORY REMAP INFORMATION
- Publication number 20100332895
- Publication date Dec 30, 2010
- Gurkirat Billing
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE FOR A HIERARCHICAL MEMORY ARCHITECTURE
- Publication number 20100318718
- Publication date Dec 16, 2010
- Sean Eilert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTONOMOUS MEMORY SUBSYSTEMS IN COMPUTING PLATFORMS
- Publication number 20100161914
- Publication date Jun 24, 2010
- Sean S. Eilert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Relocatable overlay window to access supernumerary data resources
- Publication number 20070061500
- Publication date Mar 15, 2007
- Intel Corporation
- Geoffrey Gould
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System, apparatus, and method to enable and disable a mode of opera...
- Publication number 20060136755
- Publication date Jun 22, 2006
- Shekoufeh Qawami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Communicating an address to a memory device
- Publication number 20060129701
- Publication date Jun 15, 2006
- Shekoufeh Qawami
- G11 - INFORMATION STORAGE

Mark Leinwander

Person

Patents Grantslast 30 patents

Autonomous memory architecture

XOR parity management on a physically addressable solid state drive

Autonomous memory architecture

Memory device for a hierarchical memory architecture

Using out-of-band signaling to communicate with daisy chained nonvo...

Memory device for a hierarchical memory architecture

Autonomous memory architecture

Using out-of-band signaling to communicate with daisy chained nonvo...

Memory device for a hierarchical memory architecture

Autonomous memory subsystem architecture

Switchable on-die memory error correcting engine

Memory device for a hierarchical memory architecture

Block-based storage device with a memory-mapped interface

Autonomous memory subsystem architecture

Block-based storage device with a memory-mapped interface

Switchable on-die memory error correcting engine

Switchable on-die memory error correcting engine

Non-volatile memory to store memory remap information

Selecting an integrated circuit from different integrated circuit a...

Patents Applicationslast 30 patents

AUTONOMOUS MEMORY ARCHITECTURE

MEMORY DEVICE FOR A HIERARCHICAL MEMORY ARCHITECTURE

AUTONOMOUS MEMORY ARCHITECTURE

MEMORY DEVICE FOR A HIERARCHICAL MEMORY ARCHITECTURE

MEMORY DEVICE FOR A HIERARCHICAL MEMORY ARCHITECTURE

AUTONOMOUS MEMORY SUBSYSTEM ARCHITECTURE

BLOCK-BASED STORAGE DEVICE WITH A MEMORY-MAPPED INTERFACE

SWITCHABLE ON-DIE MEMORY ERROR CORRECTING ENGINE

SWITCHABLE ON-DIE MEMORY ERROR CORRECTING ENGINE

Nonvolatile Storage with Disparate Memory Types

AUTONOMOUS MEMORY ARCHITECTURE

AUTONOMOUS SUBSYSTEM ARCHITECTURE

NON-VOLATILE MEMORY TO STORE MEMORY REMAP INFORMATION

MEMORY DEVICE FOR A HIERARCHICAL MEMORY ARCHITECTURE

AUTONOMOUS MEMORY SUBSYSTEMS IN COMPUTING PLATFORMS

Relocatable overlay window to access supernumerary data resources

System, apparatus, and method to enable and disable a mode of opera...

Communicating an address to a memory device