Michael Anthony ZAMPAGLIONE

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Word all zero memory
- Patent number 10,741,249
- Issue date Aug 11, 2020
- Synopsys, Inc.
- Michael Anthony Zampaglione
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error detection and correction in ternary content addressable memor...
- Patent number 9,762,261
- Issue date Sep 12, 2017
- eSilicon Corporation
- Michael Anthony Zampaglione
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low leakage and data retention circuitry
- Patent number 9,722,605
- Issue date Aug 1, 2017
- Conversant Intellectual Property Management Inc.
- Barry A. Hoberman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Error detection and correction in binary content addressable memory...
- Patent number 9,529,669
- Issue date Dec 27, 2016
- eSilicon Corporation
- Michael Anthony Zampaglione
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low leakage and data retention circuitry
- Patent number 9,350,349
- Issue date May 24, 2016
- Conversant Intellectual Property Management Inc.
- Barry A. Hoberman
- G11 - INFORMATION STORAGE
Information Patent Grant
Low leakage and data retention circuitry
- Patent number 8,854,077
- Issue date Oct 7, 2014
- Conversant Intellectual Property Management Inc.
- Barry A. Hoberman
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM leakage reduction circuit
- Patent number 8,416,633
- Issue date Apr 9, 2013
- Mosaid Technologies Incorporated
- Michael Anthony Zampaglione
- G11 - INFORMATION STORAGE
Information Patent Grant
Pushed-rule bit cells with new functionality
- Patent number 8,355,269
- Issue date Jan 15, 2013
- eSilicon Corporation
- Michael Anthony Zampaglione
- G11 - INFORMATION STORAGE
Information Patent Grant
Low leakage and data retention circuitry
- Patent number 8,253,438
- Issue date Aug 28, 2012
- MOSAID Technologies Incorporated
- Barry A. Hoberman
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM leakage reduction circuit
- Patent number 8,077,527
- Issue date Dec 13, 2011
- Mosaid Technologies Incorporated
- Michael Anthony Zampaglione
- G11 - INFORMATION STORAGE
Information Patent Grant
Low leakage and data retention circuitry
- Patent number 7,940,081
- Issue date May 10, 2011
- MOSAID Technologies Incorporated
- Barry A. Hoberman
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM leakage reduction circuit
- Patent number 7,684,262
- Issue date Mar 23, 2010
- Mosaid Technologies Incorporated
- Michael Anthony Zampaglione
- G11 - INFORMATION STORAGE
Information Patent Grant
Low leakage and data retention circuitry
- Patent number 7,592,837
- Issue date Sep 22, 2009
- MOSAID Technologies Corporation
- Barry A. Hoberman
- G11 - INFORMATION STORAGE
Information Patent Grant
Low leakage and data retention circuitry
- Patent number 7,443,197
- Issue date Oct 28, 2008
- Mosaid Technologies, Inc.
- Barry A. Hoberman
- G11 - INFORMATION STORAGE
Information Patent Grant
Low leakage and data retention circuitry
- Patent number 7,348,804
- Issue date Mar 25, 2008
- MOSAID Delaware, Inc.
- Barry A. Hoberman
- G11 - INFORMATION STORAGE
Information Patent Grant
Low leakage and data retention circuitry
- Patent number 7,227,383
- Issue date Jun 5, 2007
- Mosaid Delaware, Inc.
- Barry A. Hoberman
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for integrated circuit design with library cells
- Patent number 7,051,308
- Issue date May 23, 2006
- Virtual Silicon Technology, Inc.
- Michael J. McManus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for design of integrated circuits
- Patent number 6,839,882
- Issue date Jan 4, 2005
- Virtual Silicon Technology, Inc.
- Michael J. McManus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for integrated circuit design with a software...
- Patent number 6,766,496
- Issue date Jul 20, 2004
- Virtual Silicon Technology, Inc.
- Michael J. McManus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic optimization of a compiled memory structure based on user...
- Patent number 5,625,797
- Issue date Apr 29, 1997
- VLSI Technology, Inc.
- Thomas V. Ferry
- G11 - INFORMATION STORAGE
Information Patent Grant
Estimation of pin-to-pin timing for compiled blocks
- Patent number 5,596,505
- Issue date Jan 21, 1997
- VLSI Technology, Inc.
- Russell L. Steinweg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory compiler with multiple selectable core elements
- Patent number 5,349,552
- Issue date Sep 20, 1994
- VLSI Technology, Inc.
- Michael A. Zampaglione
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for compensating for bit line delays in semico...
- Patent number 5,245,584
- Issue date Sep 14, 1993
- VLSI Technology, Inc.
- Michael A. Zampaglione
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital output buffer and method with slew rate control and reduced...
- Patent number 5,231,311
- Issue date Jul 27, 1993
- VLSI Technology, Inc.
- Thomas V. Ferry
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reduced switching noise output buffer using diode for quick turn-off
- Patent number 5,111,075
- Issue date May 5, 1992
- VLSI Technology, Inc.
- Thomas V. Ferry
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
LOW LEAKAGE AND DATA RETENTION CIRCUITRY
- Publication number 20160315615
- Publication date Oct 27, 2016
- Conversant Intellectual Property Management Inc.
- Barry A. Hoberman
- G11 - INFORMATION STORAGE
Information Patent Application
Error Detection and Correction in Binary Content Addressable Memory...
- Publication number 20150095740
- Publication date Apr 2, 2015
- eSilicon Corporation
- Michael Anthony Zampaglione
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Error Detection and Correction in Ternary Content Addressable Memor...
- Publication number 20150095738
- Publication date Apr 2, 2015
- eSilicon Corporation
- Michael Anthony Zampaglione
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low Leakage and Data Retention Circuitry
- Publication number 20140375354
- Publication date Dec 25, 2014
- Barry A. Hoberman
- G11 - INFORMATION STORAGE
Information Patent Application
LOW LEAKAGE AND DATA RETENTION CIRCUITRY
- Publication number 20130027125
- Publication date Jan 31, 2013
- Barry A. Hoberman
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM LEAKAGE REDUCTION CIRCUIT
- Publication number 20120057416
- Publication date Mar 8, 2012
- Michael Anthony ZAMPAGLIONE
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low Leakage and Data Retention Circuitry
- Publication number 20110260785
- Publication date Oct 27, 2011
- MOSAID TECHNOLOGIES INCORPORATED
- Barry A. Hoberman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SRAM LEAKAGE REDUCTION CIRCUIT
- Publication number 20100232236
- Publication date Sep 16, 2010
- MOSAID TECHNOLOGIES INCORPORATED
- Michael Anthony ZAMPAGLIONE
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW LEAKAGE AND DATA RETENTION CIRCUITRY
- Publication number 20100060319
- Publication date Mar 11, 2010
- MOSAID Technologies Corporation
- Barry A. Hoberman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low leakage and data retention circuitry
- Publication number 20090027080
- Publication date Jan 29, 2009
- MOSAID Technologies, Inc.
- Barry A. Hoberman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low leakage and data retention circuitry
- Publication number 20080084775
- Publication date Apr 10, 2008
- Virtual Silicon Technology, Inc.
- Barry B. Hoberman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SRAM LEAKAGE REDUCTION CIRCUIT
- Publication number 20070252623
- Publication date Nov 1, 2007
- MOSAID TECHNOLOGIES CORPORATION
- Michael Anthony Zampaglione
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low leakage and data retention circuitry
- Publication number 20070176639
- Publication date Aug 2, 2007
- MOSAID Delaware, Inc.
- Barry A. Hoberman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low leakage and data retention circuitry
- Publication number 20050184758
- Publication date Aug 25, 2005
- Virtual Silicon Technology, Inc.
- Barry A. Hoberman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and apparatus for design of integrated circuits
- Publication number 20030023937
- Publication date Jan 30, 2003
- Michael J. McManus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for integrated circuit design with library cells
- Publication number 20030023935
- Publication date Jan 30, 2003
- Michael J. McManus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for integrated circuit design with a software...
- Publication number 20030023936
- Publication date Jan 30, 2003
- Michael J. McManus
- G06 - COMPUTING CALCULATING COUNTING

Michael Anthony ZAMPAGLIONE

Person

Patents Grantslast 30 patents

Word all zero memory

Error detection and correction in ternary content addressable memor...

Low leakage and data retention circuitry

Error detection and correction in binary content addressable memory...

Low leakage and data retention circuitry

Low leakage and data retention circuitry

SRAM leakage reduction circuit

Pushed-rule bit cells with new functionality

Low leakage and data retention circuitry

SRAM leakage reduction circuit

Low leakage and data retention circuitry

SRAM leakage reduction circuit

Low leakage and data retention circuitry

Low leakage and data retention circuitry

Low leakage and data retention circuitry

Low leakage and data retention circuitry

Method and apparatus for integrated circuit design with library cells

Method and apparatus for design of integrated circuits

Method and apparatus for integrated circuit design with a software...

Automatic optimization of a compiled memory structure based on user...

Estimation of pin-to-pin timing for compiled blocks

Memory compiler with multiple selectable core elements

Method and apparatus for compensating for bit line delays in semico...

Digital output buffer and method with slew rate control and reduced...

Reduced switching noise output buffer using diode for quick turn-off

Patents Applicationslast 30 patents

LOW LEAKAGE AND DATA RETENTION CIRCUITRY

Error Detection and Correction in Binary Content Addressable Memory...

Error Detection and Correction in Ternary Content Addressable Memor...

Low Leakage and Data Retention Circuitry

LOW LEAKAGE AND DATA RETENTION CIRCUITRY

SRAM LEAKAGE REDUCTION CIRCUIT

Low Leakage and Data Retention Circuitry

SRAM LEAKAGE REDUCTION CIRCUIT

LOW LEAKAGE AND DATA RETENTION CIRCUITRY

Low leakage and data retention circuitry

Low leakage and data retention circuitry

SRAM LEAKAGE REDUCTION CIRCUIT

Low leakage and data retention circuitry

Low leakage and data retention circuitry

Method and apparatus for design of integrated circuits

Method and apparatus for integrated circuit design with library cells

Method and apparatus for integrated circuit design with a software...