Michael Catherwood

Person

Georgetown, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multibit shift instruction
- Patent number 12,093,688
- Issue date Sep 17, 2024
- Microchip Technology Incorporated
- Michael Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector fetch bus error handling
- Patent number 12,001,270
- Issue date Jun 4, 2024
- Microchip Technology Incorporated
- Michael Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Central processing unit with enhanced instruction set
- Patent number 10,983,931
- Issue date Apr 20, 2021
- Microchip Technology Incorporated
- Michael Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Central processing unit with DSP engine and enhanced context switch...
- Patent number 10,802,866
- Issue date Oct 13, 2020
- Microchip Technology Incorporated
- Michael Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for protecting program memory for processing c...
- Patent number 10,776,292
- Issue date Sep 15, 2020
- Microchip Technology Incorporated
- Michael Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Run time ECC error injection scheme for hardware validation
- Patent number 10,248,521
- Issue date Apr 2, 2019
- Microchip Technology Incorporated
- Michael Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable mailbox data buffer apparatus
- Patent number 10,120,815
- Issue date Nov 6, 2018
- Microchip Technology Incorporated
- Michael Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for generating cross-core breakpoints in a multi-...
- Patent number 10,102,050
- Issue date Oct 16, 2018
- Microchip Technology Incorporated
- Bryan Kris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-pin microcontroller device with multiple independent microcontr...
- Patent number 10,002,102
- Issue date Jun 19, 2018
- Microchip Technology Incorporated
- Bryan Kris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-pin microcontroller device with multiple independent microcontr...
- Patent number 10,002,103
- Issue date Jun 19, 2018
- Microchip Technology Incorporated
- Bryan Kris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual boot panel SWAP mechanism
- Patent number 9,858,083
- Issue date Jan 2, 2018
- Microchip Technology Incorporated
- Michael I. Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable CPU register hardware context swap mechanism
- Patent number 9,619,231
- Issue date Apr 11, 2017
- Microchip Technology Incorporated
- Michael I. Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data space arbiter
- Patent number 8,984,198
- Issue date Mar 17, 2015
- Microchip Technology Incorporated
- Michael I. Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Peripheral trigger generator
- Patent number 8,856,406
- Issue date Oct 7, 2014
- Microchip Technology Incorporated
- Bryan Kris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable exception processing latency
- Patent number 8,688,964
- Issue date Apr 1, 2014
- Microchip Technology Incorporated
- Michael I. Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
External device power control during low power sleep mode without c...
- Patent number 8,645,729
- Issue date Feb 4, 2014
- Microchip Technology Incorporated
- Michael Simmons
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
DSP engine with implicit mixed sign operands
- Patent number 8,495,125
- Issue date Jul 23, 2013
- Microchip Technology Incorporated
- Michael I. Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register pointer trap to prevent errors due to an invalid pointer v...
- Patent number 7,966,480
- Issue date Jun 21, 2011
- Microchip Technology Incorporated
- Michael I. Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual mode arithmetic saturation processing
- Patent number 7,467,178
- Issue date Dec 16, 2008
- Microchip Technology Incorporated
- Michael I. Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modified Harvard architecture processor having data memory space ma...
- Patent number 7,243,372
- Issue date Jul 10, 2007
- Microchip Technology Incorporated
- Michael Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced power option
- Patent number 7,020,788
- Issue date Mar 28, 2006
- Microchip Technology Incorporated
- Michael I. Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modified Harvard architecture processor having data memory space ma...
- Patent number 7,007,172
- Issue date Feb 28, 2006
- Microchip Technology Incorporated
- Michael Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Repeat instruction with interrupt
- Patent number 6,976,158
- Issue date Dec 13, 2005
- Microchip Technology Incorporated
- Michael Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Maximally negative signed fractional number multiplication
- Patent number 6,952,711
- Issue date Oct 4, 2005
- Microchip Technology Incorporated
- Michael I. Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Euclidean distance instructions
- Patent number 6,934,728
- Issue date Aug 23, 2005
- Microchip Technology Incorporated
- Michael I. Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modified Harvard architecture processor having program memory space...
- Patent number 6,728,856
- Issue date Apr 27, 2004
- Microchip Technology Incorporated
- James H. Grosbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modulo addressing based on absolute offset
- Patent number 6,604,169
- Issue date Aug 5, 2003
- Microchip Technology Incorporated
- Michael I. Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically reconfigurable data space
- Patent number 6,601,160
- Issue date Jul 29, 2003
- Microchip Technology Incorporated
- Michael Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for providing erasing and programming protecti...
- Patent number 5,890,191
- Issue date Mar 30, 1999
- Motorola, Inc.
- George L. Espinor
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for determining wait states on a per cycle bas...
- Patent number 5,854,944
- Issue date Dec 29, 1998
- Motorola, Inc.
- Michael I. Catherwood
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Atomic Instruction Set and Architecture with Bus Arbitration Locking
- Publication number 20230342158
- Publication date Oct 26, 2023
- MICROCHIP TECHNOLOGY INCORPORATED
- Robert Ellis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIBIT SHIFT INSTRUCTION
- Publication number 20230176867
- Publication date Jun 8, 2023
- MICROCHIP TECHNOLOGY INCORPORATED
- Michael Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR MANAGING INTERRUPT PRIORITY LEVELS
- Publication number 20230176898
- Publication date Jun 8, 2023
- MICROCHIP TECHNOLOGY INCORPORATED
- Michael Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIBIT SHIFT INSTRUCTION
- Publication number 20230176866
- Publication date Jun 8, 2023
- MICROCHIP TECHNOLOGY INCORPORATED
- Michael Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Accelerated Read, Modify, Write Operations
- Publication number 20230176738
- Publication date Jun 8, 2023
- MICROCHIP TECHNOLOGY INCORPORATED
- Michael Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VECTOR FETCH BUS ERROR HANDLING
- Publication number 20230176937
- Publication date Jun 8, 2023
- MICROCHIP TECHNOLOGY INCORPORATED
- Michael Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR PROTECTING PROGRAM MEMORY FOR PROCESSING C...
- Publication number 20190188163
- Publication date Jun 20, 2019
- MICROCHIP TECHNOLOGY INCORPORATED
- Michael Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Configurable Mailbox Data Buffer Apparatus
- Publication number 20160371200
- Publication date Dec 22, 2016
- MICROCHIP TECHNOLOGY INCORPORATED
- Michael Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Central Processing Unit With DSP Engine And Enhanced Context Switch...
- Publication number 20160321075
- Publication date Nov 3, 2016
- MICROCHIP TECHNOLOGY INCORPORATED
- Michael Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Central Processing Unit With Enhanced Instruction Set
- Publication number 20160321202
- Publication date Nov 3, 2016
- MICROCHIP TECHNOLOGY INCORPORATED
- Michael Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Run Time ECC Error Injection Scheme for Hardware Validation
- Publication number 20160292059
- Publication date Oct 6, 2016
- MICROCHIP TECHNOLOGY INCORPORATED
- Michael Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low-Pin Microcontroller Device With Multiple Independent Microcontr...
- Publication number 20160267047
- Publication date Sep 15, 2016
- MICROCHIP TECHNOLOGY INCORPORATED
- Bryan Kris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low-Pin Microcontroller Device With Multiple Independent Microcontr...
- Publication number 20160267046
- Publication date Sep 15, 2016
- MICROCHIP TECHNOLOGY INCORPORATED
- Bryan Kris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable CPU Register Hardware Context Swap Mechanism
- Publication number 20150019847
- Publication date Jan 15, 2015
- MICROCHIP TECHNOLOGY INCORPORATED
- Michael I. Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dual Boot Panel SWAP Mechanism
- Publication number 20140281465
- Publication date Sep 18, 2014
- Michael I. Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERIPHERAL TRIGGER GENERATOR
- Publication number 20140075052
- Publication date Mar 13, 2014
- Bryan Kris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXTERNAL DEVICE POWER CONTROL DURING LOW POWER SLEEP MODE WITHOUT C...
- Publication number 20110179297
- Publication date Jul 21, 2011
- MICROCHIP TECHNOLOGY INCORPORATED
- Michael Simmons
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Data Space Arbiter
- Publication number 20110022756
- Publication date Jan 27, 2011
- MICROCHIP TECHNOLOGY INCORPORATED
- Michael I. Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE EXCEPTION PROCESSING LATENCY
- Publication number 20110016295
- Publication date Jan 20, 2011
- MICROCHIP TECHNOLOGY INCORPORATED
- Michael I. Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DSP Engine with Implicit Mixed Sign Operands
- Publication number 20100306292
- Publication date Dec 2, 2010
- MICROCHIP TECHNOLOGY INCORPORATED
- Michael I. Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Modified Harvard architecture processor having data memory space ma...
- Publication number 20050210284
- Publication date Sep 22, 2005
- MICROCHIP TECHNOLOGY INCORPORATED
- Michael Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Register pointer trap
- Publication number 20050172109
- Publication date Aug 4, 2005
- MICROCHIP TECHNOLOGY INCORPORATED
- Michael I. Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Microcontroller instruction set
- Publication number 20050166036
- Publication date Jul 28, 2005
- Microchip Technology Inc.
- Michael I. Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reduced power option
- Publication number 20030126484
- Publication date Jul 3, 2003
- Michael I. Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Digital signal controller instruction set and architecture
- Publication number 20030061464
- Publication date Mar 27, 2003
- Michael I. Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamically reconfigurable data space
- Publication number 20030028743
- Publication date Feb 6, 2003
- Michael Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low overhead interrupt
- Publication number 20030028696
- Publication date Feb 6, 2003
- Michael Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Shadow register array control instructions
- Publication number 20030023836
- Publication date Jan 30, 2003
- Michael Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-precision barrel shifting
- Publication number 20030005269
- Publication date Jan 2, 2003
- Joshua M. Conner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Modified harvard architecture processor having data memory space ma...
- Publication number 20030005245
- Publication date Jan 2, 2003
- Michael Catherwood
- G06 - COMPUTING CALCULATING COUNTING

Michael Catherwood

Person

Patents Grantslast 30 patents

Multibit shift instruction

Vector fetch bus error handling

Central processing unit with enhanced instruction set

Central processing unit with DSP engine and enhanced context switch...

Apparatus and method for protecting program memory for processing c...

Run time ECC error injection scheme for hardware validation

Configurable mailbox data buffer apparatus

System and method for generating cross-core breakpoints in a multi-...

Low-pin microcontroller device with multiple independent microcontr...

Low-pin microcontroller device with multiple independent microcontr...

Dual boot panel SWAP mechanism

Programmable CPU register hardware context swap mechanism

Data space arbiter

Peripheral trigger generator

Programmable exception processing latency

External device power control during low power sleep mode without c...

DSP engine with implicit mixed sign operands

Register pointer trap to prevent errors due to an invalid pointer v...

Dual mode arithmetic saturation processing

Modified Harvard architecture processor having data memory space ma...

Reduced power option

Modified Harvard architecture processor having data memory space ma...

Repeat instruction with interrupt

Maximally negative signed fractional number multiplication

Euclidean distance instructions

Modified Harvard architecture processor having program memory space...

Modulo addressing based on absolute offset

Dynamically reconfigurable data space

Method and apparatus for providing erasing and programming protecti...

Method and apparatus for determining wait states on a per cycle bas...

Patents Applicationslast 30 patents

Atomic Instruction Set and Architecture with Bus Arbitration Locking

MULTIBIT SHIFT INSTRUCTION

SYSTEMS AND METHODS FOR MANAGING INTERRUPT PRIORITY LEVELS

MULTIBIT SHIFT INSTRUCTION

Accelerated Read, Modify, Write Operations

VECTOR FETCH BUS ERROR HANDLING

APPARATUS AND METHOD FOR PROTECTING PROGRAM MEMORY FOR PROCESSING C...

Configurable Mailbox Data Buffer Apparatus

Central Processing Unit With DSP Engine And Enhanced Context Switch...

Central Processing Unit With Enhanced Instruction Set

Run Time ECC Error Injection Scheme for Hardware Validation

Low-Pin Microcontroller Device With Multiple Independent Microcontr...

Low-Pin Microcontroller Device With Multiple Independent Microcontr...

Programmable CPU Register Hardware Context Swap Mechanism

Dual Boot Panel SWAP Mechanism

PERIPHERAL TRIGGER GENERATOR

EXTERNAL DEVICE POWER CONTROL DURING LOW POWER SLEEP MODE WITHOUT C...

Data Space Arbiter

PROGRAMMABLE EXCEPTION PROCESSING LATENCY

DSP Engine with Implicit Mixed Sign Operands

Modified Harvard architecture processor having data memory space ma...

Register pointer trap

Microcontroller instruction set

Reduced power option

Digital signal controller instruction set and architecture

Dynamically reconfigurable data space

Low overhead interrupt

Shadow register array control instructions

Multi-precision barrel shifting

Modified harvard architecture processor having data memory space ma...