Mirmajid Seyyedy

Person

Boise, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Hybrid MRAM array structure and operation
- Patent number 8,451,642
- Issue date May 28, 2013
- Micron Technology, Inc.
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE
Information Patent Grant
Hybrid MRAM array structure and operation
- Patent number 8,154,004
- Issue date Apr 10, 2012
- Micron Technology, Inc.
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked memory cell structure and method of forming such a structure
- Patent number 7,978,491
- Issue date Jul 12, 2011
- Micron Technology, Inc.
- Hasan Nejad
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Hybrid MRAM array structure and operation
- Patent number 7,732,221
- Issue date Jun 8, 2010
- Micron Technology, Inc.
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for testing a memory device with compressed da...
- Patent number 7,562,268
- Issue date Jul 14, 2009
- Micron Technology, Inc.
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked columnar 1T-nMTj MRAM structure and its method of formation...
- Patent number 7,440,339
- Issue date Oct 21, 2008
- Micron Technology, Inc.
- Hasan Nejad
- G11 - INFORMATION STORAGE
Information Patent Grant
Magnetic tunneling junction antifuse device
- Patent number 7,405,966
- Issue date Jul 29, 2008
- Micron Technology, Inc.
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked columnar 1T-nMTJ MRAM structure and its method of formation...
- Patent number 7,339,811
- Issue date Mar 4, 2008
- Micron Technology, Inc.
- Hasan Nejad
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked 1T-nmemory cell structure
- Patent number 7,339,812
- Issue date Mar 4, 2008
- Micron Technology, Inc.
- Hasan Nejad
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked 1T-nMTJ MRAM structure
- Patent number 7,330,367
- Issue date Feb 12, 2008
- Micron Technology, Inc.
- Hasan Nejad
- G11 - INFORMATION STORAGE
Information Patent Grant
Columnar 1T-N memory cell structure
- Patent number 7,209,378
- Issue date Apr 24, 2007
- Micron Technology, Inc.
- Hasan Nejad
- G11 - INFORMATION STORAGE
Information Patent Grant
Magnetic tunneling junction antifuse device
- Patent number 7,176,065
- Issue date Feb 13, 2007
- Micron Technology, Inc.
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuits with contemporaneously formed array electrodes...
- Patent number 7,126,200
- Issue date Oct 24, 2006
- Micron Technology, Inc.
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked 1T-nmemory cell structure
- Patent number 7,042,749
- Issue date May 9, 2006
- Micron Technology, Inc.
- Hasan Nejad
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked columnar 1T-nMTJ structure and its method of formation and...
- Patent number 7,023,743
- Issue date Apr 4, 2006
- Micron Technology, Inc.
- Hasan Nejad
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for testing a memory device with compressed da...
- Patent number 6,976,195
- Issue date Dec 13, 2005
- Micron Technology, Inc.
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked 1T-nMTJ MRAM structure
- Patent number 6,940,748
- Issue date Sep 6, 2005
- Micron Technology, Inc.
- Hasan Nejad
- G11 - INFORMATION STORAGE
Information Patent Grant
Magnetic tunneling junction antifuse device
- Patent number 6,919,613
- Issue date Jul 19, 2005
- Micron Technology, Inc.
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked 1T-nMTJ MRAM structure
- Patent number 6,882,566
- Issue date Apr 19, 2005
- Micron Technology, Inc.
- Hasan Nejad
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked columnar resistive memory structure and its method of forma...
- Patent number 6,882,553
- Issue date Apr 19, 2005
- Micron Technology Inc.
- Hasan Nejad
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked columnar 1T-nMTJ MRAM structure and its method of formation...
- Patent number 6,879,516
- Issue date Apr 12, 2005
- Micron Technology Inc.
- Hasan Nejad
- G11 - INFORMATION STORAGE
Information Patent Grant
Flip chip technique for chip assembly
- Patent number 6,831,361
- Issue date Dec 14, 2004
- Micron Technology, Inc.
- Mirmajid Seyyedy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flip-chip technique for chip assembly
- Patent number 6,780,675
- Issue date Aug 24, 2004
- Micron Technology, Inc.
- Mirmajid Seyyedy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid MRAM array structure and operation
- Patent number 6,754,124
- Issue date Jun 22, 2004
- Micron Technology, Inc.
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE
Information Patent Grant
Magnetic tunneling junction antifuse device
- Patent number 6,751,149
- Issue date Jun 15, 2004
- Micron Technology, Inc.
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE
Information Patent Grant
Single ended row select for a MRAM device
- Patent number 6,751,117
- Issue date Jun 15, 2004
- Micron Technology, Inc.
- Tom W. Voshell
- G11 - INFORMATION STORAGE
Information Patent Grant
Error correction chip for memory applications
- Patent number 6,725,414
- Issue date Apr 20, 2004
- Micron Technology, Inc.
- Mirmajid Seyyedy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single ended row select for a MRAM device
- Patent number 6,574,137
- Issue date Jun 3, 2003
- Micron Technology, Inc.
- Tom W. Voshell
- G11 - INFORMATION STORAGE
Information Patent Grant
Redundancy antifuse bank for a memory device
- Patent number 6,424,584
- Issue date Jul 23, 2002
- Micron Technology, Inc.
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE
Information Patent Grant
Column select latch for SDRAM
- Patent number 6,320,816
- Issue date Nov 20, 2001
- Micron Technology, Inc.
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
HYBRID MRAM ARRAY STRUCTURE AND OPERATION
- Publication number 20120188812
- Publication date Jul 26, 2012
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE
Information Patent Application
HYBRID MRAR ARRAY STRUCTURE AND OPERATION
- Publication number 20100044668
- Publication date Feb 25, 2010
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE
Information Patent Application
Stacked 1T-nmemory cell structure
- Publication number 20080180982
- Publication date Jul 31, 2008
- Hasan Nejad
- G11 - INFORMATION STORAGE
Information Patent Application
MAGNETIC TUNNELING JUNCTION ANTIFUSE DEVICE
- Publication number 20070127303
- Publication date Jun 7, 2007
- Micron Technology, Inc.
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUITS WITH CONTEMPORANEOUSLY FORMED ARRAY ELECTRODES...
- Publication number 20070029630
- Publication date Feb 8, 2007
- Micron Technology, Inc.
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE
Information Patent Application
1T-nmemory cell structure and its method of formation and operation
- Publication number 20060171224
- Publication date Aug 3, 2006
- Hasan Nejad
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated circuits with contemporaneously formed array electrodes...
- Publication number 20060099797
- Publication date May 11, 2006
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for testing a memory device with compressed da...
- Publication number 20060090108
- Publication date Apr 27, 2006
- Micron Technology, Inc.
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE
Information Patent Application
Stacked columnar 1T-nMTj MRAM structure and its method of formation...
- Publication number 20050226038
- Publication date Oct 13, 2005
- Micron Technology, Inc.
- Hasan Nejad
- G11 - INFORMATION STORAGE
Information Patent Application
Stacked columnar 1T-nMTJ MRAM structure and its method of formation...
- Publication number 20050226037
- Publication date Oct 13, 2005
- Micron Technology, Inc.
- Hasan Nejad
- G11 - INFORMATION STORAGE
Information Patent Application
Stacked 1T-nmemory cell structure
- Publication number 20050226041
- Publication date Oct 13, 2005
- Micron Technology, Inc.
- Hasan Nejad
- G11 - INFORMATION STORAGE
Information Patent Application
Magnetic tunneling junction antifuse device
- Publication number 20050190620
- Publication date Sep 1, 2005
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE
Information Patent Application
Columnar 1T-nMemory cell structure and its method of formation and...
- Publication number 20050162883
- Publication date Jul 28, 2005
- Hasan Nejad
- G11 - INFORMATION STORAGE
Information Patent Application
Stacked IT-nMTJ MRAM structure
- Publication number 20050162898
- Publication date Jul 28, 2005
- Hasan Nejad
- G11 - INFORMATION STORAGE
Information Patent Application
Stacked 1T-nMTJ MRAM structure
- Publication number 20040264242
- Publication date Dec 30, 2004
- Hasan Nejad
- G11 - INFORMATION STORAGE
Information Patent Application
Hybrid MRAM array structure and operation
- Publication number 20040213044
- Publication date Oct 28, 2004
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE
Information Patent Application
Magnetic tunneling junction antifuse device
- Publication number 20040188799
- Publication date Sep 30, 2004
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE
Information Patent Application
Stacked columnar 1T-nMTJ MRAM structure and its method of formation...
- Publication number 20040165421
- Publication date Aug 26, 2004
- Hasan Nejad
- G11 - INFORMATION STORAGE
Information Patent Application
Stacked columnar 1T-nMTJ MRAM structure and its method of formation...
- Publication number 20040165461
- Publication date Aug 26, 2004
- Hasan Nejad
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated circuits with contemporaneously formed array electrodes...
- Publication number 20040160795
- Publication date Aug 19, 2004
- Micron Technology, Inc.
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE
Information Patent Application
Stacked columnar 1T-nMTJ MRAM structure and its method of formation...
- Publication number 20040057276
- Publication date Mar 25, 2004
- Hasan Nejad
- G11 - INFORMATION STORAGE
Information Patent Application
Hybrid MRAM array structure and operation
- Publication number 20030227795
- Publication date Dec 11, 2003
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE
Information Patent Application
Stacked 1T-nmemory cell structure
- Publication number 20030223292
- Publication date Dec 4, 2003
- Hasan Nejad
- G11 - INFORMATION STORAGE
Information Patent Application
STACKED 1T-NMTJ MRAM STRUCTURE
- Publication number 20030214835
- Publication date Nov 20, 2003
- Hasan Nejad
- G11 - INFORMATION STORAGE
Information Patent Application
Single ended row select for a MRAM device
- Publication number 20030202401
- Publication date Oct 30, 2003
- Tom W. Voshell
- G11 - INFORMATION STORAGE
Information Patent Application
Magnetic tunneling junction antifuse device
- Publication number 20030179601
- Publication date Sep 25, 2003
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE
Information Patent Application
Single ended row select for a MRAM device
- Publication number 20030043619
- Publication date Mar 6, 2003
- Tom W. Voshell
- G11 - INFORMATION STORAGE
Information Patent Application
Error correction chip for memory applications
- Publication number 20020049951
- Publication date Apr 25, 2002
- Micron Technology, Inc.
- Mirmajid Seyyedy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Flip chip technique for chip assembly
- Publication number 20010050432
- Publication date Dec 13, 2001
- Mirmajid Seyyedy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Column select latch for SDRAM
- Publication number 20010009529
- Publication date Jul 26, 2001
- Micron Technology, Inc.
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE

Mirmajid Seyyedy

Person

Patents Grantslast 30 patents

Hybrid MRAM array structure and operation

Hybrid MRAM array structure and operation

Stacked memory cell structure and method of forming such a structure

Hybrid MRAM array structure and operation

Method and apparatus for testing a memory device with compressed da...

Stacked columnar 1T-nMTj MRAM structure and its method of formation...

Magnetic tunneling junction antifuse device

Stacked columnar 1T-nMTJ MRAM structure and its method of formation...

Stacked 1T-nmemory cell structure

Stacked 1T-nMTJ MRAM structure

Columnar 1T-N memory cell structure

Magnetic tunneling junction antifuse device

Integrated circuits with contemporaneously formed array electrodes...

Stacked 1T-nmemory cell structure

Stacked columnar 1T-nMTJ structure and its method of formation and...

Method and apparatus for testing a memory device with compressed da...

Stacked 1T-nMTJ MRAM structure

Magnetic tunneling junction antifuse device

Stacked 1T-nMTJ MRAM structure

Stacked columnar resistive memory structure and its method of forma...

Stacked columnar 1T-nMTJ MRAM structure and its method of formation...

Flip chip technique for chip assembly

Flip-chip technique for chip assembly

Hybrid MRAM array structure and operation

Magnetic tunneling junction antifuse device

Single ended row select for a MRAM device

Error correction chip for memory applications

Single ended row select for a MRAM device

Redundancy antifuse bank for a memory device

Column select latch for SDRAM

Patents Applicationslast 30 patents

HYBRID MRAM ARRAY STRUCTURE AND OPERATION

HYBRID MRAR ARRAY STRUCTURE AND OPERATION

Stacked 1T-nmemory cell structure

MAGNETIC TUNNELING JUNCTION ANTIFUSE DEVICE

INTEGRATED CIRCUITS WITH CONTEMPORANEOUSLY FORMED ARRAY ELECTRODES...

1T-nmemory cell structure and its method of formation and operation

Integrated circuits with contemporaneously formed array electrodes...

Method and apparatus for testing a memory device with compressed da...

Stacked columnar 1T-nMTj MRAM structure and its method of formation...

Stacked columnar 1T-nMTJ MRAM structure and its method of formation...

Stacked 1T-nmemory cell structure

Magnetic tunneling junction antifuse device

Columnar 1T-nMemory cell structure and its method of formation and...

Stacked IT-nMTJ MRAM structure

Stacked 1T-nMTJ MRAM structure

Hybrid MRAM array structure and operation

Magnetic tunneling junction antifuse device

Stacked columnar 1T-nMTJ MRAM structure and its method of formation...

Stacked columnar 1T-nMTJ MRAM structure and its method of formation...

Integrated circuits with contemporaneously formed array electrodes...

Stacked columnar 1T-nMTJ MRAM structure and its method of formation...

Hybrid MRAM array structure and operation

Stacked 1T-nmemory cell structure

STACKED 1T-NMTJ MRAM STRUCTURE

Single ended row select for a MRAM device

Magnetic tunneling junction antifuse device

Single ended row select for a MRAM device

Error correction chip for memory applications

Flip chip technique for chip assembly

Column select latch for SDRAM