Mourad El Baraji

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Systems and methods utilizing serial and parallel configurations of...
- Patent number 10,937,478
- Issue date Mar 2, 2021
- Spin Memory, Inc.
- Kadriye Deniz Bozdag
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory array with individually trimmable sense amplifiers
- Patent number 10,930,332
- Issue date Feb 23, 2021
- Spin Memory, Inc.
- Susmita Karmakar
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array with horizontal source line and a virtual source line
- Patent number 10,891,997
- Issue date Jan 12, 2021
- Spin Memory, Inc.
- Neal Berger
- G11 - INFORMATION STORAGE
Information Patent Grant
Over-voltage write operation of tunnel magnet-resistance (“TMR”) me...
- Patent number 10,656,994
- Issue date May 19, 2020
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with a plurality of memory banks where each memory ba...
- Patent number 10,628,316
- Issue date Apr 21, 2020
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-port random access memory
- Patent number 10,546,624
- Issue date Jan 28, 2020
- Spin Memory, Inc.
- Mourad El Baraji
- G11 - INFORMATION STORAGE
Information Patent Grant
On-the-fly bit failure detection and bit redundancy remapping techn...
- Patent number 10,529,439
- Issue date Jan 7, 2020
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to...
- Patent number 10,489,245
- Issue date Nov 26, 2019
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Forcing bits as bad to widen the window between the distributions o...
- Patent number 10,481,976
- Issue date Nov 19, 2019
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with a dual Y-multiplexer structure for performing tw...
- Patent number 10,460,781
- Issue date Oct 29, 2019
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory instruction pipeline with a pre-read stage for a write opera...
- Patent number 10,446,210
- Issue date Oct 15, 2019
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of flushing the contents of a dynamic redundancy register to...
- Patent number 10,437,723
- Issue date Oct 8, 2019
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of processing incomplete memory operations in a memory devic...
- Patent number 10,437,491
- Issue date Oct 8, 2019
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of reading data from a memory device using multiple levels o...
- Patent number 10,424,393
- Issue date Sep 24, 2019
- Spin Memory, Inc.
- Mourad El Baraji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods utilizing serial configurations of magnetic mem...
- Patent number 10,403,343
- Issue date Sep 3, 2019
- SPIN MEMORY, INC.
- Kadriye Deniz Bozdag
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Perpendicular source and bit lines for an MRAM array
- Patent number 10,395,711
- Issue date Aug 27, 2019
- Spin Memory, Inc.
- Neal Berger
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array with horizontal source line and sacrificial bitline pe...
- Patent number 10,395,712
- Issue date Aug 27, 2019
- Spin Memory, Inc.
- Neal Berger
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device using levels of dynamic redundancy registers for writ...
- Patent number 10,366,775
- Issue date Jul 30, 2019
- Spin Memory, Inc.
- Mourad El Baraji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device with dynamic redundancy registers
- Patent number 10,366,774
- Issue date Jul 30, 2019
- Spin Memory, Inc.
- Mourad El Baraji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
AC current pre-charge write-assist in orthogonal STT-MRAM
- Patent number 10,360,961
- Issue date Jul 23, 2019
- Spin Memory, Inc.
- Michail Tzoufras
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory array with individually trimmable sense amplifiers
- Patent number 10,360,962
- Issue date Jul 23, 2019
- Spin Memory, Inc.
- Susmita Karmakar
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of writing contents in memory during a power up sequence usi...
- Patent number 10,360,964
- Issue date Jul 23, 2019
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for bipolar memory write-verify
- Patent number 10,347,314
- Issue date Jul 9, 2019
- Spin Memory, Inc.
- Neal Berger
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods utilizing parallel configurations of magnetic m...
- Patent number 10,347,308
- Issue date Jul 9, 2019
- SPIN MEMORY, INC.
- Kadriye Deniz Bozdag
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microwave write-assist in orthogonal STT-MRAM
- Patent number 10,255,962
- Issue date Apr 9, 2019
- Spin Memory, Inc.
- Mourad El Baraji
- G11 - INFORMATION STORAGE
Information Patent Grant
AC current write-assist in orthogonal STT-MRAM
- Patent number 10,236,048
- Issue date Mar 19, 2019
- Spin Memory, Inc.
- Michail Tzoufras
- G11 - INFORMATION STORAGE
Information Patent Grant
Microwave write-assist in series-interconnected orthogonal STT-MRAM...
- Patent number 10,229,724
- Issue date Mar 12, 2019
- Spin Memory, Inc.
- Mourad El Baraji
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory instruction pipeline with an additional write stage in a mem...
- Patent number 10,192,601
- Issue date Jan 29, 2019
- SPIN TRANSFER TECHNOLOGIES, INC.
- Neal Berger
- G11 - INFORMATION STORAGE
Information Patent Grant
Smart cache design to prevent overflow for a memory device with a d...
- Patent number 10,192,602
- Issue date Jan 29, 2019
- SPIN TRANSFER TECHNOLOGIES, INC.
- Neal Berger
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for bipolar memory write-verify
- Patent number 10,163,479
- Issue date Dec 25, 2018
- SPIN TRANSFER TECHNOLOGIES, INC.
- Neal Berger
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Systems and Methods Utilizing Parallel Configurations of Magnetic M...
- Publication number 20200043535
- Publication date Feb 6, 2020
- Spin Memory, Inc.
- Kadriye Deniz Bozdag
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARRAY WITH INDIVIDUALLY TRIMMABLE SENSE AMPLIFIERS
- Publication number 20190348097
- Publication date Nov 14, 2019
- Spin Memory, Inc.
- Susmita KARMAKAR
- G11 - INFORMATION STORAGE
Information Patent Application
Systems and Methods Utilizing Serial Configurations of Magnetic Mem...
- Publication number 20190206465
- Publication date Jul 4, 2019
- Spin Transfer Technologies
- Kadriye Deniz Bozdag
- G11 - INFORMATION STORAGE
Information Patent Application
PERPENDICULAR SOURCE AND BIT LINES FOR AN MRAM ARRAY
- Publication number 20190206470
- Publication date Jul 4, 2019
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
Systems and Methods Utilizing Parallel Configurations of Magnetic M...
- Publication number 20190206939
- Publication date Jul 4, 2019
- Spin Memory, Inc.
- Kadriye Deniz Bozdag
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-PORT RANDOM ACCESS MEMORY
- Publication number 20190206468
- Publication date Jul 4, 2019
- Spin Transfer Technologies, Inc.
- Mourad EL-BARAJI
- G11 - INFORMATION STORAGE
Information Patent Application
AC CURRENT PRE-CHARGE WRITE-ASSIST IN ORTHOGONAL STT-MRAM
- Publication number 20190206462
- Publication date Jul 4, 2019
- Spin Memory, Inc.
- Michail TZOUFRAS
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARRAY WITH INDIVIDUALLY TRIMMABLE SENSE AMPLIFIERS
- Publication number 20190206467
- Publication date Jul 4, 2019
- Spin Transfer Technologies, Inc.
- Susmita KARMAKAR
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARRAY WITH HORIZONTAL SOURCE LINE AND SACRIFICIAL BITLINE PE...
- Publication number 20190206473
- Publication date Jul 4, 2019
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARRAY WITH HORIZONTAL SOURCE LINE AND A VIRTUAL SOURCE LINE
- Publication number 20190206471
- Publication date Jul 4, 2019
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
ON-THE-FLY BIT FAILURE DETECTION AND BIT REDUNDANCY REMAPPING TECHN...
- Publication number 20190122746
- Publication date Apr 25, 2019
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
OVER-VOLTAGE WRITE OPERATION OF TUNNEL MAGNET-RESISTANCE ("TMR") ME...
- Publication number 20190121694
- Publication date Apr 25, 2019
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
FORCING BITS AS BAD TO WIDEN THE WINDOW BETWEEN THE DISTRIBUTIONS O...
- Publication number 20190121692
- Publication date Apr 25, 2019
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
FORCING STUCK BITS, WATERFALL BITS, SHUNT BITS AND LOW TMR BITS TO...
- Publication number 20190121693
- Publication date Apr 25, 2019
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF WRITING CONTENTS IN MEMORY DURING A POWER UP SEQUENCE USI...
- Publication number 20180122447
- Publication date May 3, 2018
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY INSTRUCTION PIPELINE WITH A PRE-READ STAGE FOR A WRITE OPERA...
- Publication number 20180122448
- Publication date May 3, 2018
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE WITH A PLURALITY OF MEMORY BANKS WHERE EACH MEMORY BA...
- Publication number 20180121361
- Publication date May 3, 2018
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF FLUSHING THE CONTENTS OF A DYNAMIC REDUNDANCY REGISTER TO...
- Publication number 20180121355
- Publication date May 3, 2018
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY INSTRUCTION PIPELINE WITH AN ADDITIONAL WRITE STAGE IN A MEM...
- Publication number 20180122449
- Publication date May 3, 2018
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH A DUAL Y-MULTIPLEXER STRUCTURE FOR PERFORMING TW...
- Publication number 20180122446
- Publication date May 3, 2018
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
SMART CACHE DESIGN TO PREVENT OVERFLOW FOR A MEMORY DEVICE WITH A D...
- Publication number 20180122450
- Publication date May 3, 2018
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF PROCESSING INCOMPLETED MEMORY OPERATIONS IN A MEMORY DEVI...
- Publication number 20180121117
- Publication date May 3, 2018
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF READING DATA FROM A MEMORY DEVICE USING DYNAMIC REDUNDANC...
- Publication number 20180114589
- Publication date Apr 26, 2018
- Spin Transfer Technologies, Inc.
- Mourad EL BARAJI
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE USING DYNAMIC REDUNDANCY REGISTERS
- Publication number 20180114590
- Publication date Apr 26, 2018
- Spin Transfer Technologies, Inc.
- Mourad EL BARAJI
- G11 - INFORMATION STORAGE
Information Patent Application
DEVICE WITH DYNAMIC REDUNDANCY REGISTERS
- Publication number 20180090226
- Publication date Mar 29, 2018
- Spin Transfer Technologies, Inc.
- Mourad EL BARAJI
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR BIPOLAR MEMORY WRITE-VERIFY
- Publication number 20170365317
- Publication date Dec 21, 2017
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR BIPOLAR MEMORY WRITE-VERIFY
- Publication number 20170047107
- Publication date Feb 16, 2017
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Devices with Magnetic Random Access Memory (MRAM) Cells and...
- Publication number 20140361392
- Publication date Dec 11, 2014
- CROCUS TECHNOLOGY INC.
- Neal Berger
- G11 - INFORMATION STORAGE
Information Patent Application
Apparatus, System, and Method for Matching Patterns with an Ultra F...
- Publication number 20140195883
- Publication date Jul 10, 2014
- CROCUS TECHNOLOGY INC.
- Bertrand F. Cambou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Devices with Magnetic Random Access Memory (MRAM) Cells and...
- Publication number 20140110802
- Publication date Apr 24, 2014
- CROCUS TECHNOLOGY, INC.,
- Neal Berger
- G11 - INFORMATION STORAGE

Mourad El Baraji

Person

Patents Grantslast 30 patents

Systems and methods utilizing serial and parallel configurations of...

Memory array with individually trimmable sense amplifiers

Memory array with horizontal source line and a virtual source line

Over-voltage write operation of tunnel magnet-resistance (“TMR”) me...

Memory device with a plurality of memory banks where each memory ba...

Multi-port random access memory

On-the-fly bit failure detection and bit redundancy remapping techn...

Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to...

Forcing bits as bad to widen the window between the distributions o...

Memory device with a dual Y-multiplexer structure for performing tw...

Memory instruction pipeline with a pre-read stage for a write opera...

Method of flushing the contents of a dynamic redundancy register to...

Method of processing incomplete memory operations in a memory devic...

Method of reading data from a memory device using multiple levels o...

Systems and methods utilizing serial configurations of magnetic mem...

Perpendicular source and bit lines for an MRAM array

Memory array with horizontal source line and sacrificial bitline pe...

Memory device using levels of dynamic redundancy registers for writ...

Device with dynamic redundancy registers

AC current pre-charge write-assist in orthogonal STT-MRAM

Memory array with individually trimmable sense amplifiers

Method of writing contents in memory during a power up sequence usi...

Method and apparatus for bipolar memory write-verify

Systems and methods utilizing parallel configurations of magnetic m...

Microwave write-assist in orthogonal STT-MRAM

AC current write-assist in orthogonal STT-MRAM

Microwave write-assist in series-interconnected orthogonal STT-MRAM...

Memory instruction pipeline with an additional write stage in a mem...

Smart cache design to prevent overflow for a memory device with a d...

Method and apparatus for bipolar memory write-verify

Patents Applicationslast 30 patents

Systems and Methods Utilizing Parallel Configurations of Magnetic M...

MEMORY ARRAY WITH INDIVIDUALLY TRIMMABLE SENSE AMPLIFIERS

Systems and Methods Utilizing Serial Configurations of Magnetic Mem...

PERPENDICULAR SOURCE AND BIT LINES FOR AN MRAM ARRAY

Systems and Methods Utilizing Parallel Configurations of Magnetic M...

MULTI-PORT RANDOM ACCESS MEMORY

AC CURRENT PRE-CHARGE WRITE-ASSIST IN ORTHOGONAL STT-MRAM

MEMORY ARRAY WITH INDIVIDUALLY TRIMMABLE SENSE AMPLIFIERS

MEMORY ARRAY WITH HORIZONTAL SOURCE LINE AND SACRIFICIAL BITLINE PE...

MEMORY ARRAY WITH HORIZONTAL SOURCE LINE AND A VIRTUAL SOURCE LINE

ON-THE-FLY BIT FAILURE DETECTION AND BIT REDUNDANCY REMAPPING TECHN...

OVER-VOLTAGE WRITE OPERATION OF TUNNEL MAGNET-RESISTANCE ("TMR") ME...

FORCING BITS AS BAD TO WIDEN THE WINDOW BETWEEN THE DISTRIBUTIONS O...

FORCING STUCK BITS, WATERFALL BITS, SHUNT BITS AND LOW TMR BITS TO...

METHOD OF WRITING CONTENTS IN MEMORY DURING A POWER UP SEQUENCE USI...

MEMORY INSTRUCTION PIPELINE WITH A PRE-READ STAGE FOR A WRITE OPERA...

MEMORY DEVICE WITH A PLURALITY OF MEMORY BANKS WHERE EACH MEMORY BA...

METHOD OF FLUSHING THE CONTENTS OF A DYNAMIC REDUNDANCY REGISTER TO...

MEMORY INSTRUCTION PIPELINE WITH AN ADDITIONAL WRITE STAGE IN A MEM...

MEMORY DEVICE WITH A DUAL Y-MULTIPLEXER STRUCTURE FOR PERFORMING TW...

SMART CACHE DESIGN TO PREVENT OVERFLOW FOR A MEMORY DEVICE WITH A D...

METHOD OF PROCESSING INCOMPLETED MEMORY OPERATIONS IN A MEMORY DEVI...

METHOD OF READING DATA FROM A MEMORY DEVICE USING DYNAMIC REDUNDANC...

MEMORY DEVICE USING DYNAMIC REDUNDANCY REGISTERS

DEVICE WITH DYNAMIC REDUNDANCY REGISTERS

METHOD AND APPARATUS FOR BIPOLAR MEMORY WRITE-VERIFY

METHOD AND APPARATUS FOR BIPOLAR MEMORY WRITE-VERIFY

Memory Devices with Magnetic Random Access Memory (MRAM) Cells and...

Apparatus, System, and Method for Matching Patterns with an Ultra F...

Memory Devices with Magnetic Random Access Memory (MRAM) Cells and...