Murat Kerem Akarvardar

Person

Saratoga Springs, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Tall single-fin FIN-type field effect transistor structures and met...
- Patent number 10,411,010
- Issue date Sep 10, 2019
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Composite isolation structures for a fin-type field effect transistor
- Patent number 10,297,597
- Issue date May 21, 2019
- GLOBALFOUNDRIES Inc.
- Min Gyu Sung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical field effect transistor formation with critical dimension...
- Patent number 10,217,846
- Issue date Feb 26, 2019
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrically insulated fin structure(s) with alternative channel ma...
- Patent number 10,163,677
- Issue date Dec 25, 2018
- GLOBALFOUNDRIES Inc.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and structure for SRB elastic relaxation
- Patent number 10,062,617
- Issue date Aug 28, 2018
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming fin isolation regions under tensile-strained fin...
- Patent number 10,026,659
- Issue date Jul 17, 2018
- GLOBALFOUNDRIES Inc.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Common fabrication of multiple FinFETs with different channel heights
- Patent number 9,960,257
- Issue date May 1, 2018
- GLOBALFOUNDRIES Inc.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Tall single-fin fin-type field effect transistor structures and met...
- Patent number 9,929,157
- Issue date Mar 27, 2018
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming defect-free relaxed SiGe fins
- Patent number 9,882,052
- Issue date Jan 30, 2018
- GLOBALFOUNDRIES Inc.
- Robert Judson Holt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrically insulated fin structure(s) with alternative channel ma...
- Patent number 9,881,830
- Issue date Jan 30, 2018
- GLOBALFOUNDRIES Inc.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reducing risk of punch-through in FinFET semiconductor structure
- Patent number 9,847,333
- Issue date Dec 19, 2017
- GLOBALFOUNDRIES Inc.
- Kwanyong Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bulk finFET with partial dielectric isolation featuring a punch-thr...
- Patent number 9,842,897
- Issue date Dec 12, 2017
- GLOBALFOUNDRIES Inc.
- Murat K. Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrical isolation of FinFET active region by selective oxidation...
- Patent number 9,716,174
- Issue date Jul 25, 2017
- GLOBALFOUNDRIES Inc.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thin strain relaxed buffers with multilayer film stacks
- Patent number 9,679,972
- Issue date Jun 13, 2017
- GLOBALFOUNDRIES Inc.
- Jody Fronheiser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FinFET fabrication by forming isolation trenches prior to fin forma...
- Patent number 9,601,383
- Issue date Mar 21, 2017
- GLOBALFOUNDRIES Inc.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of modulating strain in PFET and NFET FinFET semiconductor...
- Patent number 9,589,849
- Issue date Mar 7, 2017
- GLOBALFOUNDRIES Inc.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming fins for a FinFET device by forming and replacin...
- Patent number 9,590,040
- Issue date Mar 7, 2017
- GLOBALFOUNDRIES Inc.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and structure for SRB elastic relaxation
- Patent number 9,576,857
- Issue date Feb 21, 2017
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming transistor structures including forming channel...
- Patent number 9,570,588
- Issue date Feb 14, 2017
- GLOBALFOUNDRIES Inc.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned dual-height isolation for bulk FinFET
- Patent number 9,564,486
- Issue date Feb 7, 2017
- International Business Machines Corporation
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming replacement fins for a FinFET device using a tar...
- Patent number 9,536,990
- Issue date Jan 3, 2017
- GLOBALFOUNDRIES Inc.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming embedded source/drain regions on finFET devices
- Patent number 9,530,869
- Issue date Dec 27, 2016
- GLOBALFOUNDRIES Inc.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density and modular CMOS logic based on 3D stacked, independen...
- Patent number 9,515,088
- Issue date Dec 6, 2016
- GLOBALFOUNDRIES Inc.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming strained channel regions on FinFET devices by pe...
- Patent number 9,508,848
- Issue date Nov 29, 2016
- GLOBALFOUNDRIES Inc.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming strained channel regions on FinFET devices
- Patent number 9,502,507
- Issue date Nov 22, 2016
- GLOBALFOUNDRIES Inc.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming doped epitaxial SiGe material on semiconductor d...
- Patent number 9,455,140
- Issue date Sep 27, 2016
- GLOBALFOUNDRIES Inc.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming alternative channel materials on FinFET semicond...
- Patent number 9,425,289
- Issue date Aug 23, 2016
- GLOBALFOUNDRIES Inc.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FinFET semiconductor device with isolated fins made of alternative...
- Patent number 9,425,315
- Issue date Aug 23, 2016
- GLOBALFOUNDRIES Inc.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming replacement gate structures on FinFET devices an...
- Patent number 9,412,839
- Issue date Aug 9, 2016
- GLOBALFOUNDRIES Inc.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FinFET device including a uniform silicon alloy fin
- Patent number 9,406,803
- Issue date Aug 2, 2016
- GLOBALFOUNDRIES Inc.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
TALL SINGLE-FIN FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURES AND MET...
- Publication number 20180182757
- Publication date Jun 28, 2018
- GLOBALFOUNDRIES INC.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRICALLY INSULATED FIN STRUCTURE(S) WITH ALTERNATIVE CHANNEL MA...
- Publication number 20180138079
- Publication date May 17, 2018
- Murat Kerem AKARVARDAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING DEFECT-FREE RELAXED SiGe FINS
- Publication number 20180130656
- Publication date May 10, 2018
- GLOBALFOUNDRIES INC.
- Judson Robert Holt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMPOSITE ISOLATION STRUCTURES FOR A FIN-TYPE FIELD EFFECT TRANSISTOR
- Publication number 20180096998
- Publication date Apr 5, 2018
- GLOBALFOUNDRIES INC.
- Min Gyu Sung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING DEFECT-FREE RELAXED SIGE FINS
- Publication number 20180006155
- Publication date Jan 4, 2018
- GLOBALFOUNDRIES INC.
- Robert Judson HOLT
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND STRUCTURE FOR SRB ELASTIC RELAXATION
- Publication number 20170256462
- Publication date Sep 7, 2017
- GLOBALFOUNDRIES INC.
- Ruilong XIE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD, APPARATUS, AND SYSTEM FOR STACKED CMOS LOGIC CIRCUITS ON FINS
- Publication number 20170133406
- Publication date May 11, 2017
- GLOBALFOUNDRIES INC.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING REPLACEMENT FINS FOR A FINFET DEVICE USING A TAR...
- Publication number 20160351681
- Publication date Dec 1, 2016
- GLOBALFOUNDRIES INC.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERFACE PASSIVATION LAYERS AND METHODS OF FABRICATING
- Publication number 20160343806
- Publication date Nov 24, 2016
- GLOBALFOUNDRIES INC.
- Shariq SIDDIQUI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BULK FINFET WITH PARTIAL DIELECTRIC ISOLATION FEATURING A PUNCH-THR...
- Publication number 20160284802
- Publication date Sep 29, 2016
- GLOBALFOUNDRIES INC.
- Murat K. Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING EMBEDDED SOURCE/DRAIN REGIONS ON FINFET DEVICES
- Publication number 20160268399
- Publication date Sep 15, 2016
- GLOBALFOUNDRIES INC.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMMON FABRICATION OF MULTIPLE FINFETs WITH DIFFERENT CHANNEL HEIGHTS
- Publication number 20160268400
- Publication date Sep 15, 2016
- GLOBALFOUNDRIES INC.
- Murat Kerem AKARVARDAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCING RISK OF PUNCH-THROUGH IN FINFET SEMICONDUCTOR STRUCTURE
- Publication number 20160268260
- Publication date Sep 15, 2016
- GLOBALFOUNDRIES INC.
- Kwanyong LIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF MODULATING STRAIN IN PFET AND NFET FINFET SEMICONDUCTOR...
- Publication number 20160254195
- Publication date Sep 1, 2016
- GLOBALFOUNDRIES INC.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHANNEL LAST REPLACEMENT FLOW FOR BULK FINFETS
- Publication number 20160247919
- Publication date Aug 25, 2016
- GLOBALFOUNDRIES INC.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING FIN ISOLATION REGIONS UNDER TENSILE-STRAINED FIN...
- Publication number 20160225676
- Publication date Aug 4, 2016
- GLOBALFOUNDRIES INC.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRICALLY INSULATED FIN STRUCTURE(S) WITH ALTERNATIVE CHANNEL MA...
- Publication number 20160197004
- Publication date Jul 7, 2016
- GLOBALFOUNDRIES INC.
- Murat Kerem AKARVARDAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING TRANSISTOR STRUCTURES
- Publication number 20160190289
- Publication date Jun 30, 2016
- GLOBALFOUNDRIES INC.
- Murat Kerem AKARVARDAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FINFET DEVICE INCLUDING A UNIFORM SILICON ALLOY FIN
- Publication number 20160190323
- Publication date Jun 30, 2016
- GLOBALFOUNDRIES INC.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING REPLACEMENT GATE STRUCTURES ON FINFET DEVICES AN...
- Publication number 20160133720
- Publication date May 12, 2016
- GLOBALFOUNDRIES INC.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING DOPED EPITAXIAL SiGe MATERIAL ON SEMICONDUCTOR D...
- Publication number 20160118251
- Publication date Apr 28, 2016
- GLOBALFOUNDRIES INC.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FINFET SEMICONDUCTOR DEVICE WITH ISOLATED FINS MADE OF ALTERNATIVE...
- Publication number 20160064544
- Publication date Mar 3, 2016
- GLOBALFOUNDRIES INC.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING ALTERNATIVE CHANNEL MATERIALS ON FINFET SEMICOND...
- Publication number 20160064526
- Publication date Mar 3, 2016
- GLOBALFOUNDRIES INC.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING METASTABLE REPLACEMENT FINS FOR A FINFET SEMICON...
- Publication number 20160064250
- Publication date Mar 3, 2016
- GLOBALFOUNDRIES INC.
- Ajey P. Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RETROGRADE DOPED LAYER FOR DEVICE ISOLATION
- Publication number 20160035728
- Publication date Feb 4, 2016
- GLOBALFOUNDRIES INC.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL-WIDTH FIN STRUCTURE FOR FINFETS DEVICES
- Publication number 20160027775
- Publication date Jan 28, 2016
- GLOBALFOUNDRIES INC.
- Murat Kerem AKARVARDAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING FINS FOR A FINFET DEVICE BY FORMING AND REPLACIN...
- Publication number 20160027895
- Publication date Jan 28, 2016
- GLOBALFOUNDRIES INC.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED DUAL-HEIGHT ISOLATION FOR BULK FINFET
- Publication number 20150372080
- Publication date Dec 24, 2015
- International Business Machines Corporation
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING EPITAXIAL SEMICONDUCTOR CLADDING MATERIAL ON FIN...
- Publication number 20150318169
- Publication date Nov 5, 2015
- Yi Qi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING SUBSTANTIALLY DEFECT-FREE, FULLY-STRAINED SILICO...
- Publication number 20150279973
- Publication date Oct 1, 2015
- GLOBALFOUNDRIES INC.
- Murat Kerem AKARVARDAR
- H01 - BASIC ELECTRIC ELEMENTS

Murat Kerem Akarvardar

Person

Patents Grantslast 30 patents

Tall single-fin FIN-type field effect transistor structures and met...

Composite isolation structures for a fin-type field effect transistor

Vertical field effect transistor formation with critical dimension...

Electrically insulated fin structure(s) with alternative channel ma...

Method and structure for SRB elastic relaxation

Methods of forming fin isolation regions under tensile-strained fin...

Common fabrication of multiple FinFETs with different channel heights

Tall single-fin fin-type field effect transistor structures and met...

Forming defect-free relaxed SiGe fins

Electrically insulated fin structure(s) with alternative channel ma...

Reducing risk of punch-through in FinFET semiconductor structure

Bulk finFET with partial dielectric isolation featuring a punch-thr...

Electrical isolation of FinFET active region by selective oxidation...

Thin strain relaxed buffers with multilayer film stacks

FinFET fabrication by forming isolation trenches prior to fin forma...

Methods of modulating strain in PFET and NFET FinFET semiconductor...

Methods of forming fins for a FinFET device by forming and replacin...

Method and structure for SRB elastic relaxation

Methods of forming transistor structures including forming channel...

Self-aligned dual-height isolation for bulk FinFET

Methods of forming replacement fins for a FinFET device using a tar...

Methods of forming embedded source/drain regions on finFET devices

High density and modular CMOS logic based on 3D stacked, independen...

Methods of forming strained channel regions on FinFET devices by pe...

Methods of forming strained channel regions on FinFET devices

Methods of forming doped epitaxial SiGe material on semiconductor d...

Methods of forming alternative channel materials on FinFET semicond...

FinFET semiconductor device with isolated fins made of alternative...

Methods of forming replacement gate structures on FinFET devices an...

FinFET device including a uniform silicon alloy fin

Patents Applicationslast 30 patents

TALL SINGLE-FIN FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURES AND MET...

ELECTRICALLY INSULATED FIN STRUCTURE(S) WITH ALTERNATIVE CHANNEL MA...

FORMING DEFECT-FREE RELAXED SiGe FINS

COMPOSITE ISOLATION STRUCTURES FOR A FIN-TYPE FIELD EFFECT TRANSISTOR

FORMING DEFECT-FREE RELAXED SIGE FINS

METHOD AND STRUCTURE FOR SRB ELASTIC RELAXATION

METHOD, APPARATUS, AND SYSTEM FOR STACKED CMOS LOGIC CIRCUITS ON FINS

METHODS OF FORMING REPLACEMENT FINS FOR A FINFET DEVICE USING A TAR...

INTERFACE PASSIVATION LAYERS AND METHODS OF FABRICATING

BULK FINFET WITH PARTIAL DIELECTRIC ISOLATION FEATURING A PUNCH-THR...

METHODS OF FORMING EMBEDDED SOURCE/DRAIN REGIONS ON FINFET DEVICES

COMMON FABRICATION OF MULTIPLE FINFETs WITH DIFFERENT CHANNEL HEIGHTS

REDUCING RISK OF PUNCH-THROUGH IN FINFET SEMICONDUCTOR STRUCTURE

METHODS OF MODULATING STRAIN IN PFET AND NFET FINFET SEMICONDUCTOR...

CHANNEL LAST REPLACEMENT FLOW FOR BULK FINFETS

METHODS OF FORMING FIN ISOLATION REGIONS UNDER TENSILE-STRAINED FIN...

ELECTRICALLY INSULATED FIN STRUCTURE(S) WITH ALTERNATIVE CHANNEL MA...

METHODS OF FORMING TRANSISTOR STRUCTURES

FINFET DEVICE INCLUDING A UNIFORM SILICON ALLOY FIN

METHODS OF FORMING REPLACEMENT GATE STRUCTURES ON FINFET DEVICES AN...

METHODS OF FORMING DOPED EPITAXIAL SiGe MATERIAL ON SEMICONDUCTOR D...

FINFET SEMICONDUCTOR DEVICE WITH ISOLATED FINS MADE OF ALTERNATIVE...

METHODS OF FORMING ALTERNATIVE CHANNEL MATERIALS ON FINFET SEMICOND...

METHODS OF FORMING METASTABLE REPLACEMENT FINS FOR A FINFET SEMICON...

RETROGRADE DOPED LAYER FOR DEVICE ISOLATION

DUAL-WIDTH FIN STRUCTURE FOR FINFETS DEVICES

METHODS OF FORMING FINS FOR A FINFET DEVICE BY FORMING AND REPLACIN...

SELF-ALIGNED DUAL-HEIGHT ISOLATION FOR BULK FINFET

METHODS OF FORMING EPITAXIAL SEMICONDUCTOR CLADDING MATERIAL ON FIN...

METHODS OF FORMING SUBSTANTIALLY DEFECT-FREE, FULLY-STRAINED SILICO...