Patent Application
20160027775
The present disclosure relates to a fin formation process for fin-type field-effect transistor (FinFET) devices. The present disclosure is particularly applicable to 14 nanometer (nm) technology nodes and beyond.
With the increasing miniaturization of integrated circuits (ICs), fin width needs to be scaled in each technology node; however, decreasing the fin width increases the external resistance (Rext) of the device.
An example flow for forming a FinFET device with scaled fins starts with forming the fins 101 and 103, e.g., made of silicon (Si) or silicon germanium (SiGe), as depicted in
Since the considered fin widths for advanced FinFET technologies are well below 10 nm, the ungated portion of the fins under the spacers result in a very high external resistance. On the other hand, the fin width under the gate should be kept very narrow to guarantee an adequate electrostatic integrity for very short channel (10-20 nm) devices. A need therefore exists for methodology enabling a narrow fin width under the gate and a wider width under the spacers and the resulting device.
An aspect of the present disclosure is a method of forming fins of Si or high Ge concentration SiGe with a narrow width under the gate and a wider width under the spacers.
Another aspect of the present disclosure is a FinFET device having Si or high Ge concentration SiGe fins with a narrow width under the gate and a wider width under the spacers.
Additional aspects and other features of the present disclosure will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present disclosure. The advantages of the present disclosure may be realized and obtained as particularly pointed out in the appended claims.
According to the present disclosure, some technical effects may be achieved in part by a method including: forming Si fins; forming a dummy gate, with a dummy oxide thereunder and a nitride HM on top, on the Si fins, the dummy gate formed perpendicular to the Si fins; forming a nitride spacer on each side of the dummy gate; filling oxide in-between adjacent gates and planarizing the oxide; removing the nitride HM and dummy gate, forming a channel between the nitride spacers; oxidizing the Si fins in the channel; removing the dummy oxide and oxidized portions of Si fins; and forming a RMG on the Si fins between the nitride spacers.
Aspects of the present disclosure include forming Si fins to a width of 10 nm to 20 nm. Further aspects include oxidizing the Si fins until each of the Si fins has a width of 6 nm to 8 nm in the channel. Another aspect includes oxidizing the Si fins at a temperature of 800° C. to 1000° C.
Another aspect of the present disclosure is a method including: forming SiGe fins; forming a dummy gate, with a dummy oxide thereunder and a nitride HM on top, on the SiGe fins, the poly dummy gate formed perpendicular to the SiGe fins; forming a nitride spacer on each side of the dummy gate; filling oxide in-between adjacent gates and planarizing the oxide; removing the nitride HM and dummy gate, forming a channel between the nitride spacers; oxidizing the SiGe fins in the channel so that the Ge percentage increases due to condensation; removing the dummy oxide and oxidized portions of the SiGe fins; and forming a RMG on the SiGe fins between the nitride spacers.
Aspects of the present disclosure include forming the SiGe fins with 15% to 40% Ge. Other aspects include forming the SiGe fins to a width of 10 nm to 20 nm. Another aspect includes oxidizing the SiGe fins until each of the SiGe fins has a width of 6 nm to 8 nm in the channel. Additional aspects include oxidizing the SiGe fins at a temperature of 800° C. to 950° C. Other aspects include oxidizing the SiGe fins for 2 mins. to 60 mins. depending on the temperature and initial Ge %. Further aspects include condensing the SiGe fins until the concentration of Ge is 30% to 80%.
Another aspect of the present disclosure is a device including: fins, each fin having a first portion between two second portions, the first portion having a narrower width than the second portions; a RMG formed on the first portion of the fins; and a nitride spacer on each side of the RMG on the second portions. Aspects of the device include the first portion being formed to a width of 6 nm to 8 nm and the second portions being formed to a width of 10 nm to 20 nm. Other aspects include the fins being formed of silicon Si. Further aspects include the fins being formed of SiGe. Another aspect includes the concentration of Ge relative to Si being 30% to 80%.
Additional aspects and technical effects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present disclosure are described simply by way of illustration of the best mode contemplated to carry out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:
In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.”
The present disclosure addresses and solves the current problem of increased Rext upon forming FinFet devices with a scaled fin width. When applied to fins made of low percentage (10-40%) SiGe, the proposed method allows an increase in Ge % to 70-80% by condensation in addition to decreasing the external resistance.
Methodology in accordance with embodiments of the present disclosure includes forming Si fins. A dummy gate (with a dummy oxide underneath and a nitride HM on top) is formed on the Si fins, the dummy gate formed perpendicular to the Si fins. A nitride spacer is formed on each side of the dummy gate. Oxide is filled in-between adjacent gates and planarized and the nitride HM and dummy gate are removed, forming a channel between the nitride spacers. The Si fins are oxidized in the channel. The dummy oxide and oxidized portions of the Si fins are removed, and a RMG is formed on the Si fins between the nitride spacers.
Still other aspects, features, and technical effects will be readily apparent to those skilled in this art from the following detailed description, wherein preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated. The disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
Adverting to
Next, a dummy gate 301 (with a dummy oxide underneath and a nitride HM on top) is formed on the fins 201 and 203, perpendicular to the fins 201 and 203, as depicted in
Adverting to
In the case where the fins 201 and 203 are formed of Si, the fins 201 and 203 may, for example, be oxidized at a temperature of 800° C. to 1000° C. for 3 mins. to 30 mins. In the case where the fins 201 and 203 are formed of SiGe, the fins 201 and 203 may, for example, be oxidized at a temperature of 800° C. to 950° for 2 mins. to 60 mins. depending on the temperature and initial Ge %, since the oxidation results in condensation of the Ge such that the Ge concentration increases. In other words, in the case where the fins 201 and 203 are composed of SiGe, the fins 201 and 203 may, for example, be oxidized and, therefore, condensed until the concentration of Ge is increased to 30% to 80% (not shown for illustrative convenience). In particular, whereas high Ge concentration SiGe fins are often subjected to harsh STI densification anneals, e.g., greater than 1000° C. for 30 mins. to 60 mins., as well as an activation anneal, e.g., greater than 1000° C. for a few seconds, the thermal budget post condensation at the RMG module is less than 450° C. Consequently, the initial low Ge concentration of fins 201 and 203, for example, can be increased late in the process flow such that some of the thermal budget related issues are mitigated and compatibility with the silicon baseline is maximized.
The embodiments of the present disclosure can achieve several technical effects including a scaled fin width under the gate and a wider fin width under the gate spacers to simultaneously meet good electrostatics and low external resistance. In addition, high Ge concentration SiGe fins may be achieved while mitigating thermal budget related issues. Embodiments of the present disclosure enjoy utility in various industrial applications as, for example, microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, gaming systems, and digital cameras.
In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.
