Nader Radjy

Person

Palo Alto, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Silicided shallow junction formation and structure with high and lo...
- Patent number 6,011,272
- Issue date Jan 4, 2000
- Advanced Micro Devices, Inc.
- Farrokh Omid-Zohoor
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nonvolatile memory structure for programmable logic devices
- Patent number 5,978,272
- Issue date Nov 2, 1999
- Advanced Micro Devices, Inc.
- Hao Fang
- G11 - INFORMATION STORAGE
Information Patent Grant
Silicided shallow junction transistor formation and structure with...
- Patent number 5,973,372
- Issue date Oct 26, 1999
- Farrokh Omid-Zohoor
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method for programming PMOS memory cells
- Patent number 5,966,329
- Issue date Oct 12, 1999
- Programmable Microelectronics Corporation
- Ching-Hsiang Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile PMOS two transistor memory cell and array
- Patent number 5,912,842
- Issue date Jun 15, 1999
- Programmable Microelectronics Corp.
- Shang-De Ted Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash EEPROM array with floating substrate erase operation
- Patent number 5,598,369
- Issue date Jan 28, 1997
- Advanced Micro Devices, Inc.
- Jian Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Reduced column leakage during programming for a flash memory array
- Patent number 5,579,261
- Issue date Nov 26, 1996
- Advanced Micro Devices, Inc.
- Nader Radjy
- G11 - INFORMATION STORAGE
Information Patent Grant
Multistepped threshold convergence for a flash memory array
- Patent number 5,576,991
- Issue date Nov 19, 1996
- Advanced Micro Devices, Inc.
- Nader Radjy
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash EEPROM array with floating substrate erase operation
- Patent number 5,561,620
- Issue date Oct 1, 1996
- Advanced Micro Devices, Inc.
- Jian Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Adjustable threshold voltage conversion circuit
- Patent number 5,521,867
- Issue date May 28, 1996
- Advanced Micro Devices, Inc.
- Jian Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for improving the endurance of floating gate d...
- Patent number 5,231,602
- Issue date Jul 27, 1993
- Advanced Micro Devices, Inc.
- Nader A. Radjy
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of page-mode programming flash EEPROM cell arrays
- Patent number 5,191,556
- Issue date Mar 2, 1993
- Advanced Micro Devices, Inc.
- Nader Radjy
- G11 - INFORMATION STORAGE
Information Patent Grant
Optimized electrically erasable cell for minimum read disturb and a...
- Patent number 5,101,378
- Issue date Mar 31, 1992
- Advanced Micro Devices, Inc.
- Nader A. Radjy
- G11 - INFORMATION STORAGE
Information Patent Grant
Optimized electrically erasable PLA cell for minimum read disturb
- Patent number 5,005,155
- Issue date Apr 2, 1991
- Advanced Micro Devices, Inc.
- Nader A. Radjy
- G11 - INFORMATION STORAGE
Information Patent Grant
Optimized E.sup.2 pal cell for minimum read disturb
- Patent number 4,935,648
- Issue date Jun 19, 1990
- Advance Micro Devices, Inc.
- Nader A. Radjy
- G11 - INFORMATION STORAGE

Nader Radjy

Person

Patents Grantslast 30 patents

Silicided shallow junction formation and structure with high and lo...

Nonvolatile memory structure for programmable logic devices

Silicided shallow junction transistor formation and structure with...

Apparatus and method for programming PMOS memory cells

Nonvolatile PMOS two transistor memory cell and array

Flash EEPROM array with floating substrate erase operation

Reduced column leakage during programming for a flash memory array

Multistepped threshold convergence for a flash memory array

Flash EEPROM array with floating substrate erase operation

Adjustable threshold voltage conversion circuit

Apparatus and method for improving the endurance of floating gate d...

Method of page-mode programming flash EEPROM cell arrays

Optimized electrically erasable cell for minimum read disturb and a...

Optimized electrically erasable PLA cell for minimum read disturb

Optimized E.sup.2 pal cell for minimum read disturb