Paul Ying-Fung Wu

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Secure communications using loop-based authentication flow
- Patent number 12,081,531
- Issue date Sep 3, 2024
- JONETIX CORPORATION
- Paul Ying-Fung Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Encryption and decryption techniques using shuffle function
- Patent number 12,069,038
- Issue date Aug 20, 2024
- JONETIX CORPORATION
- Paul Ying-Fung Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Secure hardware signature and related methods and applications
- Patent number 12,032,676
- Issue date Jul 9, 2024
- JONETIX CORPORATION
- Paul Ying-Fung Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Secure communications using loop-based authentication flow
- Patent number 11,595,368
- Issue date Feb 28, 2023
- JONETIX CORPORATION
- Paul Ying-Fung Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Secure hardware signature and related methods and applications
- Patent number 11,544,371
- Issue date Jan 3, 2023
- JONETIX CORPORATION
- Paul Ying-Fung Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Encryption and decryption techniques using shuffle function
- Patent number 11,516,201
- Issue date Nov 29, 2022
- JONETIX CORPORATION
- Paul Ying-Fung Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Encryption and decryption techniques using shuffle function
- Patent number 10,931,658
- Issue date Feb 23, 2021
- Jonetix Corporation
- Paul Ying-Fung Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Secure hardware signature and related methods and applications
- Patent number 10,891,366
- Issue date Jan 12, 2021
- JONETIX CORPORATION
- Paul Ying-Fung Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Secure communications using loop-based authentication flow
- Patent number 10,742,622
- Issue date Aug 11, 2020
- JONETIX CORPORATION
- Paul Ying-Fung Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Encryption and decryption techniques using shuffle function
- Patent number 10,419,416
- Issue date Sep 17, 2019
- Jonetix Corporation
- Paul Ying-Fung Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Secure communications using loop-based authentication flow
- Patent number 10,263,779
- Issue date Apr 16, 2019
- JONETIX CORPORATION
- Paul Ying-Fung Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Low insertion loss package pin structure and method
- Patent number 10,038,259
- Issue date Jul 31, 2018
- Xilinx, Inc.
- Paul Y. Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Encryption and decryption techniques using shuffle function
- Patent number 10,021,085
- Issue date Jul 10, 2018
- Jonetix Corporation
- Paul Ying-Fung Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Encryption and decryption techniques using shuffle function
- Patent number 9,635,011
- Issue date Apr 25, 2017
- Jonetix Corporation
- Paul Ying-Fung Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamic configuration of equivalent series resistance
- Patent number 9,377,802
- Issue date Jun 28, 2016
- Xilinx, Inc.
- Christopher P. Wyland
- G05 - CONTROLLING REGULATING
Information Patent Grant
Capacitors within an interposer coupled to supply and ground planes...
- Patent number 9,337,138
- Issue date May 10, 2016
- Xilinx, Inc.
- Khaldoon S. Abugharbieh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Conductor structure with integrated via element
- Patent number 9,144,150
- Issue date Sep 22, 2015
- Xilinx, Inc.
- Paul Y. Wu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Warpage management for fan-out mold packaged integrated circuit
- Patent number 9,006,030
- Issue date Apr 14, 2015
- Xilinx, Inc.
- Woon-Seong Kwon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect pattern for semiconductor packaging
- Patent number 8,743,559
- Issue date Jun 3, 2014
- Xilinx, Inc.
- Paul Y. Wu
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Air through-silicon via structure
- Patent number 8,519,542
- Issue date Aug 27, 2013
- Xilinx, Inc.
- Namhoon Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power distribution network
- Patent number 8,410,579
- Issue date Apr 2, 2013
- Xilinx, Inc.
- Atul V. Ghia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect pattern for semiconductor packaging
- Patent number 8,395,903
- Issue date Mar 12, 2013
- Xilinx, Inc.
- Paul Ying-Fung Wu
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Semiconductor device package and methods of manufacturing the same
- Patent number 8,178,962
- Issue date May 15, 2012
- Xilinx, Inc.
- Soon-Shin Chee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making metal core substrate printed circuit wiring board...
- Patent number 6,711,812
- Issue date Mar 30, 2004
- Unicap Electronics Industrial Corporation
- Jane Lu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Process and structure for manufacturing plastic chip carrier
- Patent number 6,675,472
- Issue date Jan 13, 2004
- Unicap Electronics Industrial Corporation
- Edward Huang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Ball grid array structure and method for packaging an integrated ci...
- Patent number 6,034,427
- Issue date Mar 7, 2000
- Prolinx Labs Corporation
- James J. D. Lan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for supporting one or more electronic components
- Patent number 5,987,744
- Issue date Nov 23, 1999
- Prolinx Labs Corporation
- James J. D. Lan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Antifuse interconnect between two conducting layers of a printed ci...
- Patent number 5,962,815
- Issue date Oct 5, 1999
- Prolinx Labs Corporation
- James J. D. Lan
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Programmable/reprogrammable structure using fuses and antifuses
- Patent number 5,906,043
- Issue date May 25, 1999
- Prolinx Labs Corporation
- James J. D. Lan
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method and structure to interconnect traces of two conductive layer...
- Patent number 5,906,042
- Issue date May 25, 1999
- Prolinx Labs Corporation
- James J. D. Lan
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Secure Communications Using Loop-Based Authentication Flow
- Publication number 20230362147
- Publication date Nov 9, 2023
- Jonetix Corporation
- Paul Ying-Fung Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SECURE HARDWARE SIGNATURE AND RELATED METHODS AND APPLICATIONS
- Publication number 20230281292
- Publication date Sep 7, 2023
- Jonetix Corporation
- Paul Ying-Fung Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENCRYPTION AND DECRYPTION TECHNIQUES USING SHUFFLE FUNCTION
- Publication number 20230231840
- Publication date Jul 20, 2023
- Jonetix Corporation
- Paul Ying-Fung Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PROCESSOR ARCHITECTURE AND RELATED TECHNIQUES
- Publication number 20230195943
- Publication date Jun 22, 2023
- Jonetix Corporation
- Paul Ying-Fung Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CRYPTOGRAPHIC DEVICE, SYSTEM AND METHOD THEROF
- Publication number 20230155825
- Publication date May 18, 2023
- Paul Ying-Fung WU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENCRYPTION AND DECRYPTION TECHNIQUES USING SHUFFLE FUNCTION
- Publication number 20210320910
- Publication date Oct 14, 2021
- Jonetix Corporation
- Paul Ying-Fung Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SECURE HARDWARE SIGNATURE AND RELATED METHODS AND APPLICATIONS
- Publication number 20210264014
- Publication date Aug 26, 2021
- Jonetix Corporation
- Paul Ying-Fung Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Secure Communications Using Loop-Based Authentication Flow
- Publication number 20210051139
- Publication date Feb 18, 2021
- Jonetix Corporation
- Paul Ying-Fung Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ENCRYPTION AND DECRYPTION TECHNIQUES USING SHUFFLE FUNCTION
- Publication number 20200153813
- Publication date May 14, 2020
- Jonetix Corporation
- Paul Ying-Fung Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Secure Communications Using Loop-Based Authentication Flow
- Publication number 20190260586
- Publication date Aug 22, 2019
- Jonetix Corporation
- Paul Ying-Fung Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ENCRYPTION AND DECRYPTION TECHNIQUES USING SHUFFLE FUNCTION
- Publication number 20190007390
- Publication date Jan 3, 2019
- Jonetix Corporation
- Paul Ying-Fung Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Secure Communications Using Loop-Based Authentication Flow
- Publication number 20180337782
- Publication date Nov 22, 2018
- Jonetix Corporation
- Paul Ying-Fung Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
THIN PROFILE METAL TRACE TO SUPPRESS SKIN EFFECT AND EXTEND PACKAGE...
- Publication number 20150282299
- Publication date Oct 1, 2015
- Xilinx, Inc.
- Hong Shi
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
LOW INSERTION LOSS PACKAGE PIN STRUCTURE AND METHOD
- Publication number 20150222033
- Publication date Aug 6, 2015
- Xilinx, Inc.
- Paul Y. Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE HAVING BUCKET-SHAPED UNDER-BUMP METALLIZATON A...
- Publication number 20150187715
- Publication date Jul 2, 2015
- Xilinx, Inc.
- Michael J. Hart
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-LAYER CORE ORGANIC PACKAGE SUBSTRATE
- Publication number 20140262440
- Publication date Sep 18, 2014
- Xilinx, Inc.
- Namhoon Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONDUCTOR STRUCTURE WITH INTEGRATED VIA ELEMENT
- Publication number 20130277099
- Publication date Oct 24, 2013
- Xilinx, Inc.
- Paul Y. Wu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
INTEGRATED CIRCUIT CONNECTIVITY USING FLEXIBLE CIRCUITRY
- Publication number 20130181360
- Publication date Jul 18, 2013
- Xilinx, Inc.
- Namhoon Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER DISTRIBUTION NETWORK
- Publication number 20120139083
- Publication date Jun 7, 2012
- Xilinx, Inc.
- Atul V. Ghia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
AIR THROUGH-SILICON VIA STRUCTURE
- Publication number 20120032326
- Publication date Feb 9, 2012
- Xilinx, Inc.
- Namhoon Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THROUGH-SILICON VIAS WITH LOW PARASITIC CAPACITANCE
- Publication number 20110291287
- Publication date Dec 1, 2011
- Xilinx, Inc.
- Paul Y. Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE HAVING BUCKET-SHAPED UNDER-BUMP METALLIZATION...
- Publication number 20110210443
- Publication date Sep 1, 2011
- Xilinx, Inc.
- Michael J. Hart
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Metal core substrate printed wiring board enabling thermally enhanc...
- Publication number 20040163248
- Publication date Aug 26, 2004
- Unicap Electronics Industrial Corporation
- Jane Lu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Burrless castellation via process and product for plastic chip carrier
- Publication number 20040141299
- Publication date Jul 22, 2004
- Unicap Electronics Industrial Corporation
- Edward Huang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Ergonomically shaped computer pointing device
- Publication number 20030206152
- Publication date Nov 6, 2003
- Hung-Ying Shih
- G06 - COMPUTING CALCULATING COUNTING

Paul Ying-Fung Wu

Person

Patents Grantslast 30 patents

Secure communications using loop-based authentication flow

Encryption and decryption techniques using shuffle function

Secure hardware signature and related methods and applications

Secure communications using loop-based authentication flow

Secure hardware signature and related methods and applications

Encryption and decryption techniques using shuffle function

Encryption and decryption techniques using shuffle function

Secure hardware signature and related methods and applications

Secure communications using loop-based authentication flow

Encryption and decryption techniques using shuffle function

Secure communications using loop-based authentication flow

Low insertion loss package pin structure and method

Encryption and decryption techniques using shuffle function

Encryption and decryption techniques using shuffle function

Dynamic configuration of equivalent series resistance

Capacitors within an interposer coupled to supply and ground planes...

Conductor structure with integrated via element

Warpage management for fan-out mold packaged integrated circuit

Interconnect pattern for semiconductor packaging

Air through-silicon via structure

Power distribution network

Interconnect pattern for semiconductor packaging

Semiconductor device package and methods of manufacturing the same

Method of making metal core substrate printed circuit wiring board...

Process and structure for manufacturing plastic chip carrier

Ball grid array structure and method for packaging an integrated ci...

Method for supporting one or more electronic components

Antifuse interconnect between two conducting layers of a printed ci...

Programmable/reprogrammable structure using fuses and antifuses

Method and structure to interconnect traces of two conductive layer...

Patents Applicationslast 30 patents

Secure Communications Using Loop-Based Authentication Flow

SECURE HARDWARE SIGNATURE AND RELATED METHODS AND APPLICATIONS

ENCRYPTION AND DECRYPTION TECHNIQUES USING SHUFFLE FUNCTION

PROCESSOR ARCHITECTURE AND RELATED TECHNIQUES

CRYPTOGRAPHIC DEVICE, SYSTEM AND METHOD THEROF

ENCRYPTION AND DECRYPTION TECHNIQUES USING SHUFFLE FUNCTION

SECURE HARDWARE SIGNATURE AND RELATED METHODS AND APPLICATIONS

Secure Communications Using Loop-Based Authentication Flow

ENCRYPTION AND DECRYPTION TECHNIQUES USING SHUFFLE FUNCTION

Secure Communications Using Loop-Based Authentication Flow

ENCRYPTION AND DECRYPTION TECHNIQUES USING SHUFFLE FUNCTION

Secure Communications Using Loop-Based Authentication Flow

THIN PROFILE METAL TRACE TO SUPPRESS SKIN EFFECT AND EXTEND PACKAGE...

LOW INSERTION LOSS PACKAGE PIN STRUCTURE AND METHOD

SEMICONDUCTOR DEVICE HAVING BUCKET-SHAPED UNDER-BUMP METALLIZATON A...

MULTI-LAYER CORE ORGANIC PACKAGE SUBSTRATE

CONDUCTOR STRUCTURE WITH INTEGRATED VIA ELEMENT

INTEGRATED CIRCUIT CONNECTIVITY USING FLEXIBLE CIRCUITRY

POWER DISTRIBUTION NETWORK

AIR THROUGH-SILICON VIA STRUCTURE

THROUGH-SILICON VIAS WITH LOW PARASITIC CAPACITANCE

SEMICONDUCTOR DEVICE HAVING BUCKET-SHAPED UNDER-BUMP METALLIZATION...

Metal core substrate printed wiring board enabling thermally enhanc...

Burrless castellation via process and product for plastic chip carrier

Ergonomically shaped computer pointing device