Patent Application
20110291287
An embodiment of the invention relates generally to integrated circuits, and more particularly to techniques for fabricating through-silicon vias for high-frequency applications.
For a given node technology, increasing integrated circuit (IC) size typically increases the functionality that can be included on a chip. Unfortunately, defects often scale with chip area. A large chip is more likely to incorporate a defect than is a smaller chip. Defects affect yield, and yield loss often increases with increasing chip size. Various techniques have been developed to provide large ICs at desirable yield levels.
One approach to providing large ICs is to construct a large IC out of multiple smaller ICs (dice) on a silicon interposer or to stack IC chips using through-silicon via (TSV) techniques. A silicon interposer is essentially a substrate that the dice are flip-chip bonded to after the silicon interposer has been processed to provide metal wiring and contacts. A silicon interposer typically has several patterned metal layers and intervening insulating layers connected to TSVs. Multiple IC dice are physically and electrically connected to the interposer with micro-bump arrays.
Stacked IC chips use TSV techniques to allow electrical connections to both sides of the parent IC chip. For example, one side (e.g., frontside) of the parent chip is bonded to a printed wiring board, package base, or other substrate, such as with a ball grid array, and the other side has a micro-bump or other bonding technique that a second, frequently smaller, chip(s) is bonded to. TSVs extend from the active portion of the first IC to the backside of the IC, and a microbump array or bonding pads are fabricated on the backside.
Many TSVs carry low-frequency signals or DC, such as a bias voltage or a ground return, and conventional TSVs are adequate for these applications. However, ICs that have radio-frequency (RF) or other high-frequency ports (e.g., pins or pads), or critical digital paths, such as a digital path with fast (e.g., 200 ps or less) rise or fall time, the high-frequency performance of a conventional TSV may be the limiting factor in the high-frequency or critical data path. For example, a high capacitance TSV may degrade a high-frequency signal, degrade rise/fall times of a digital signal, increase cross-talk between a signal on another TSV, or increase noise injection. Furthermore, variations in capacitance in TSVs can cause undesirable variations in device performance, whether the capacitance variations are between TSVs on a single IC or interposer, or are between TSVs on different parts.
Techniques for reducing TSV capacitance or capacitance variation are desirable.
A device according to an embodiment has a via extending from a first surface of a silicon substrate. The via has a conductor portion surrounded by a first dielectric portion. A first silicon portion is next to the first dielectric portion, and a second dielectric portion is between the first silicon portion and the silicon substrate. In a particular embodiment, the conductor portion is cylindrical, the first silicon portion surrounds the first dielectric portion, and the second dielectric portion surrounds the first substrate portion. In a further embodiment, the via includes a second silicon portion surrounding the second dielectric portion, and a third dielectric portion surrounding the second silicon portion.
In a particular embodiment, the via extends from the first surface of the silicon substrate through the silicon substrate to a second surface of the silicon substrate. In a further embodiment, a contact pad electrically connected to the conductor portion extends over the first dielectric portion and the first silicon portion, and at least partially over the second dielectric portion.
In a particular embodiment, the first dielectric portion is silicon oxide and the second dielectric portion is silicon oxide. In a further embodiment, both the first dielectric portion and the second dielectric portion are thermally grown silicon dioxide. In a yet further embodiment, a passivating oxide layer is concurrently grown on the top surface of the silicon wafer.
In a particular embodiment, the first dielectric portion has a first dielectric thickness and the second dielectric portion has a second dielectric thickness, the second dielectric thickness being not greater than twice the first dielectric thickness.
In a further embodiment, a first IC is mounted on the silicon substrate and has a signal pin electrically coupled to the via. In a particular embodiment, the IC comprises an FPGA, and in a more particular embodiment, the signal pin is a high-frequency signal pin or a high-speed digital data pin.
In another embodiment, a second IC is fabricated in the silicon substrate and the via connects the signal pin of the first IC to an active portion of the second IC. In a particular embodiment, the second IC comprises a field-programmable gate array. In a further embodiment, the second IC has a second signal pin electrically connected to a second via having a second conductor portion, a dielectric liner portion surrounding the conductor portion, a first floating silicon portion, and a dielectric ring surrounding the first floating silicon portion disposed between the first floating silicon portion and the silicon substrate.
In a particular embodiment, the silicon substrate is a silicon interposer and a capacitance between the conductor portion and the silicon substrate is not greater than 50 fF. In a particular embodiment, the silicon substrate has a bulk resistivity less than 20 Ohm-cm for use as an IC substrate or active interposer substrate.
In a particular embodiment, an interposer has a silicon substrate with a via formed within the silicon substrate. The via includes a first conductor portion with a first dielectric liner surrounding the first conductor portion. A first silicon portion surrounds the first conductor portion and a first dielectric ring surrounds the first silicon portion. A second silicon portion surrounds the first dielectric ring, and a second dielectric ring surrounds the second silicon portion.
In another embodiment, a via is fabricated in a silicon wafer by defining an etch resist pattern on a surface of the silicon wafer. A conductor pocket and at least one dielectric ring pocket in the silicon wafer separated from the conductor pocket by a silicon portion are etched in the silicon wafer. Oxide is formed on a sidewall of the conductor pocket to provide a lined conductor pocket and on sidewalls of the dielectric ring pocket. A conductor is then formed in the lined conductor pocket. In a particular embodiment, forming oxide on sidewalls of the dielectric ring pocket fills the dielectric ring pocket to form a dielectric ring surrounding the silicon portion. In an alternative embodiment, oxide is grown on the sidewalls of the dielectric ring pocket to partially fill the pocket, and the remainder of the dielectric ring pocket is filled with other dielectric material. In a further embodiment, the silicon wafer is backlapped to expose the conductor on a backside of the silicon wafer.
After the step of forming the conductor, a contact pad parallel to the surface extending from the conductor at least partially over the dielectric ring is optionally formed in a further embodiment.
In a particular embodiment, defining the etch resist pattern defines a concentric dielectric ring window around a conductor window, the concentric dielectric ring window having a width not greater than twice a thickness of oxide formed on the sidewall of the conductor pocket. In a further embodiment, defining the etch resist pattern further defines a second concentric dielectric ring window around the concentric dielectric ring window. The etching leaves a first concentric silicon portion between the conductor pocket and the concentric dielectric ring pocket and a second concentric silicon portion between the concentric dielectric ring pocket and a second concentric dielectric ring pocket.
The interposer 112 has patterned metal layers 116 fabricated on a silicon wafer portion 118. In a particular example, the silicon wafer portion 118 is a portion of a silicon wafer similar to those used in IC fabrication and the interposer is an active interposer (i.e., the interposer includes electronic devices in addition to patterned metal layers). The patterned metal layers 116 may be formed using deposition and photolithographic techniques similar to those used for IC fabrication. For example, if an IC fabrication process flow (e.g., a 90 nm node technology) defines several patterned metal layers on an IC wafer (commonly called the backend fabrication process), processes similar to those used to define the upper metal layers of the IC may be used to fabricate the patterned metal layers on the interposer wafer. Interposers typically have 1 to 4 patterned metal layers separated by intervening dielectric layers and interconnected using conductive vias, as is well known in the art of thin film, damascene or dual damascene processing.
The interposer 112 translates the fine pitch of the IC contacts on the topside of the interposer to a less fine pitch on the backside. In particular examples, the topside of the interposer has about 20,000 to about 60,000 microbump contacts, and about 10,000 to about 30,000 TSVs, depending on the size of the composite IC, the number and type of ICs mounted on the interposer, and other factors. In a particular example, the microbumps are at a 45 micron pitch and the TSVs are bumped 120 to form a bump array having a pitch of about 180 microns to about 200 microns. At least one of the TSVs is fabricated according to an embodiment of the invention. In some embodiments, several TSVs (e.g., the TSVs carrying high-frequency analog signals or high-speed digital signals) are fabricated according to one or more embodiments to couple the high-speed or high-frequency signals to a corresponding high-frequency port (i.e., bump or contact) on an IC chip. Other TSVs (e.g., TSVs carrying DC bias, ground current return, or low-frequency signals) are optionally conventional TSVs. Those of skill in the art of composite ICs appreciate that
In a particular embodiment, the first dielectric portion 306 is grown silicon oxide that is grown from silicon previously of the first silicon portion 308. Similarly, the second dielectric portion 310 is grown silicon oxide that is grown from silicon previously of the first silicon portion 308 and the bulk silicon (wafer) 302. Alternative embodiments use other dielectric materials, such as spin-on dielectric precursors, or organic materials such as polyimide. In some embodiments, at least one of the dielectric portions uses composite dielectric material, such as a relatively thin liner of thermally grown oxide on the silicon walls, and a filler material of applied dielectric material. It is generally desirable that the dielectric material(s) used for the first and second dielectric portions have a relative dielectric constant(s) less than the relative dielectric constant of silicon.
In a conventional TSV, bulk silicon extends from the dielectric liner layer (e.g., a layer similar to layer 306), and a similar contact pad would capacitively couple to the wafer (substrate) from the outer edge of the dielectric layer to the outer edge of the contact pad. Similarly, the conductor portion of a conventional TSV capacitively couples to the substrate through the relatively thin dielectric liner layer. This structure forms undesirable TSV-to-substrate capacitive coupling. Similarly, TSV-to-TSV capacitive coupling arises in TSV arrays (see, e.g.,
The second dielectric portion 310 electrically isolates the first silicon portion 308 from the bulk silicon and reduces the capacitive coupling between the conductor portion 304 of the TSV and silicon wafer 302, compared to a conventional TSV having only a dielectric liner layer separating the conductor from the bulk silicon, because the relative dielectric constant of silicon dioxide (εr=4) or other dielectric material according to an embodiment is less than the dielectric constant of silicon (εr=12), because the separation between the coupling electrodes (i.e., the conductive portion 304 and the bulk silicon 302) is increased (by the thickness of the second dielectric portion 310), and because the first silicon portion 308 basically forms an intermediate electrode in a series capacitance between the conductive portion 304 and the bulk silicon. The second dielectric portion 310 also reduces the capacitive coupling of the contact pad 316 to the bulk silicon 302 because of the reduced dielectric constant under the pad and because the capacitive coupling to the first silicon portion 308 is isolated from the bulk silicon (essentially forming series capacitances).
In a particular embodiment, the parasitic capacitance of a TSV according to an embodiment is less than 50 femto-Farads (fF) in a silicon wafer having a sheet resistivity of about 20 ohm-cm. A conventional TSV having a similarly sized conductor fabricated in the same silicon wafer has a parasitic capacitance of about 100 fF. A TSV having a parasitic capacitance of not more than 50 fF is desirable for use in conductive paths of analog signals 5 GHz or higher, and for use in conductive paths of digital signals having a rise or fall time of 200 ps or faster. In other embodiments, silicon wafers with lower sheet resistivity are used. For example, a TSV according to an embodiment in a silicon wafer having a sheet resistivity of about 1 ohm-cm has a parasitic capacitance of about 200 fF. In active TSVs, the resistivity of the wafer may be constrained by circuit requirements, thus embodiments are particularly desirable in embodiments where high-resistivity wafers are precluded.
In a particular embodiment, the annular silicon oxide rings are formed during the same process steps used to form conventional TSVs. The concentric pockets for the oxide are patterned and etched along with the pocket for the conductor and liner, and silicon oxide is grown to form the concentric oxide rings when the liner oxide is grown. For example, if w1 for the conductor and liner layers is etched to a width of about 8 microns for a liner dielectric thickness of 2.4 microns, the width w2 for the oxide rings is about 4.8 microns. Oxide grows from both walls of the pockets 507, 509 to fill with grown silicon dioxide. The conductor material would fill the remainder of pocket 504, and be about 3.2 microns thick.
Comparing conventional TSVs 610, 616, the conductor portion 611 is separated from the bulk silicon by the relatively thin liner layer 612, which results in substantially greater capacitive coupling 620 of the conductor portion 611 to the substrate. Similarly, the conventional TSVs 610, 616 also have substantially greater inter-via capacitive coupling 618 between there conductor portions 611, 614.
In TSVs 602, 604 according to an embodiment, the concentric dielectric rings surrounding the conductor (and outer dielectric liner layer, see, e.g.,
In a particular embodiment, many TSVs according to one or more embodiments are fabricated concurrently. Embodiments of interposers or ICs optionally include conventional TSVs. For example, a silicon interposer includes TSVs according to one or more embodiments for one or more high-frequency signal or high-speed data paths, and includes conventional TSVs for DC connections. Alternatively, TSVs according to one or more embodiments are used for all TSVs on a silicon interposer. In a further embodiment, a high-speed port or a high-frequency signal port of an IC mounted on a silicon interposer is connected to a TSV according to an embodiment fabricated in the silicon interposer.
The FPGA architecture includes a large number of different programmable tiles including multi-gigabit transceivers (MGTs) 801, configurable logic blocks (CLBs) 802, random access memory blocks (BRAMs) 803, input/output blocks (IOBs) 804, configuration and clocking logic (CONFIG/CLOCKS) 805, digital signal processing (DSP) blocks 806, specialized input/output blocks (I/O) 807 (e.g., configuration ports and clock ports), and other programmable logic 808 such as digital clock managers, analog-to-digital converters, system monitoring logic, and so forth. Some FPGAs also include dedicated processor blocks (PROC) 810. Horizontal areas 809 extending from the CONFIG/CLOCKS 805 column are used to distribute the clocks and configuration signals across the breadth of the FPGA 800.
In some FPGAs, each programmable tile includes a programmable interconnect element (INT) 811 having standardized connections to and from a corresponding interconnect element in each adjacent tile. Therefore, the programmable interconnect elements taken together implement the programmable interconnect structure for the illustrated FPGA. The programmable interconnect element (INT) 811 also includes the connections to and from the programmable logic element within the same tile, as shown by the examples included at the top of
For example, a CLB 802 can include a configurable logic element (CLE 812) that can be programmed to implement user logic plus a single programmable interconnect element (INT) 811. A BRAM 803 can include a BRAM logic element (BRL) 813 in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the pictured embodiment, a BRAM tile has the same height as five CLBs, but other numbers (e.g., four) can also be used. A DSP tile 806 can include a DSP logic element (DSPL) 814 in addition to an appropriate number of programmable interconnect elements. An IOB 804 can include, for example, two instances of an input/output logic element (IOL) 815 in addition to one instance of the programmable interconnect element (INT) 811. Some FPGAs utilizing the architecture illustrated in
Note that
While the present invention has been described in connection with specific embodiments, variations of these embodiments will be obvious to those of ordinary skill in the art. For example, alternative dielectric fill material, or additional concentric dielectric rings, or different types of substrates or substrate material could be used, or processing steps could be performed in a different order. Therefore, the spirit and scope of the appended claims should not be limited to the foregoing description.
