Peter J. Wright

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for associating an error in a layout with a cell
- Patent number 7,313,774
- Issue date Dec 25, 2007
- Synopsys, Inc.
- Peter J. Wright
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Design methodology for dummy lines
- Patent number 6,961,915
- Issue date Nov 1, 2005
- LSI Logic Corporation
- William M. Loh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thick traces from multiple damascene layers
- Patent number 6,830,984
- Issue date Dec 14, 2004
- LSI Logic Corporation
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nonvolatile memory cell with low doping region
- Patent number 6,828,620
- Issue date Dec 7, 2004
- Altera Corporation
- Christopher J. Pass
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low resistance metal interconnect lines and a process for fabricati...
- Patent number 6,815,342
- Issue date Nov 9, 2004
- LSI Logic Corporation
- Chuan-cheng Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit containing redundant core and peripheral contacts
- Patent number 6,710,453
- Issue date Mar 23, 2004
- LSI Logic Corporation
- Peter J. Wright
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flip chip testing
- Patent number 6,617,181
- Issue date Sep 9, 2003
- LSI Logic Corporation
- Peter J. Wright
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Voltage level shifter
- Patent number 6,614,283
- Issue date Sep 2, 2003
- LSI Logic Corporation
- Peter Joseph Wright
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Nonvolatile memory cell with low doping region
- Patent number 6,573,138
- Issue date Jun 3, 2003
- Altera Corporation
- Christopher J. Pass
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Process for improving mechanical strength of layers of low k dielec...
- Patent number 6,566,244
- Issue date May 20, 2003
- LSI Logic Corporation
- Charles E. May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low resistance gate electrodes
- Patent number 6,236,094
- Issue date May 22, 2001
- Altera Corporation
- Peter J. Wright
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of margin testing programmable interconnect cell
- Patent number 6,122,209
- Issue date Sep 19, 2000
- Altera Corporation
- Christopher J. Pass
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of forming low resistance gate electrodes
- Patent number 5,966,597
- Issue date Oct 12, 1999
- Altera Corporation
- Peter J. Wright
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable interconnect junction
- Patent number 5,949,710
- Issue date Sep 7, 1999
- Altera Corporation
- Christopher J. Pass
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method to fill via holes between two conductive layers
- Patent number 5,915,756
- Issue date Jun 29, 1999
- Altera Corporation
- Peter Wright
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned antifuse with base
- Patent number 5,903,042
- Issue date May 11, 1999
- Texas Instruments Incorporated
- Siang Ping Kwok
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test structure and method to characterize charge gain in a non-vola...
- Patent number 5,764,569
- Issue date Jun 9, 1998
- Altera Corporation
- Peter J. Wright
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of fabricating self-aligned planarized well structures
- Patent number 5,523,247
- Issue date Jun 4, 1996
- Altera Corporation
- Peter Wright
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Method and apparatus for associating an error in a layout with a cell
- Publication number 20060288318
- Publication date Dec 21, 2006
- Peter J. Wright
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Design methodology for dummy lines
- Publication number 20040088669
- Publication date May 6, 2004
- William M. Loh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Flip chip testing
- Publication number 20030211641
- Publication date Nov 13, 2003
- LSI Logic Corporation
- Peter J. Wright
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Nonvolatile memory cell with low doping region
- Publication number 20030197218
- Publication date Oct 23, 2003
- Altera Corporation
- Christopher J. Pass
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Thick traces from multiple damascene layers
- Publication number 20030157805
- Publication date Aug 21, 2003
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS

Peter J. Wright

Person

Patents Grantslast 30 patents

Method and apparatus for associating an error in a layout with a cell

Design methodology for dummy lines

Thick traces from multiple damascene layers

Nonvolatile memory cell with low doping region

Low resistance metal interconnect lines and a process for fabricati...

Integrated circuit containing redundant core and peripheral contacts

Flip chip testing

Voltage level shifter

Nonvolatile memory cell with low doping region

Process for improving mechanical strength of layers of low k dielec...

Low resistance gate electrodes

Method of margin testing programmable interconnect cell

Method of forming low resistance gate electrodes

Programmable interconnect junction

Method to fill via holes between two conductive layers

Self-aligned antifuse with base

Test structure and method to characterize charge gain in a non-vola...

Method of fabricating self-aligned planarized well structures

Patents Applicationslast 30 patents

Method and apparatus for associating an error in a layout with a cell

Design methodology for dummy lines

Flip chip testing

Nonvolatile memory cell with low doping region

Thick traces from multiple damascene layers