Peter Reichert

Person

Thousand Oaks, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
System for testing devices inside of carriers
- Patent number 10,775,408
- Issue date Sep 15, 2020
- Teradyne, Inc.
- Valquirio Nazare Carvalho
- G01 - MEASURING TESTING
Information Patent Grant
X-ray inspection of solder reflow in high-density printed circuit b...
- Patent number 8,031,929
- Issue date Oct 4, 2011
- Teradyne, Inc.
- Govindarajan T. Srinivasan
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of and system for calibration of inspection systems producin...
- Patent number 7,819,581
- Issue date Oct 26, 2010
- Teradyne, Inc.
- Govindarajan T. Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Instrument with interface for synchronization in automatic test equ...
- Patent number 7,769,559
- Issue date Aug 3, 2010
- Teradyne, Inc.
- Peter A. Reichert
- G01 - MEASURING TESTING
Information Patent Grant
Multi-stream interface for parallel test processing
- Patent number 7,673,199
- Issue date Mar 2, 2010
- Teradyne, Inc.
- Peter A. Reichert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of and system for obtaining linear data for object scanned u...
- Patent number 7,626,175
- Issue date Dec 1, 2009
- Teradyne, Inc.
- Peter A. Reichert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic test system with synchronized instruments
- Patent number 7,454,681
- Issue date Nov 18, 2008
- Teradyne, Inc.
- Peter A. Reichert
- G01 - MEASURING TESTING
Information Patent Grant
Instrument with interface for synchronization in automatic test equ...
- Patent number 7,319,936
- Issue date Jan 15, 2008
- Teradyne, Inc.
- Peter A. Reichert
- G01 - MEASURING TESTING
Information Patent Grant
Multi-stage numeric counter oscillator
- Patent number 7,064,616
- Issue date Jun 20, 2006
- Teradyne, Inc.
- Peter Reichert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock architecture for a frequency-based tester
- Patent number 6,976,183
- Issue date Dec 13, 2005
- Teradyne, Inc.
- Robert Bruce Gage
- G01 - MEASURING TESTING
Information Patent Grant
Low cost timing system for highly accurate multi-modal semiconducto...
- Patent number 6,553,529
- Issue date Apr 22, 2003
- Teradyne, Inc.
- Peter Reichert
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for testing integrated circuit chips that outp...
- Patent number 6,486,693
- Issue date Nov 26, 2002
- Teradyne, Inc.
- George Conner
- G01 - MEASURING TESTING
Information Patent Grant
Pattern generator for a packet-based memory tester
- Patent number 6,389,525
- Issue date May 14, 2002
- Teradyne, Inc.
- Peter Reichert
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory architecture for automatic test equipment using vector modul...
- Patent number 6,286,120
- Issue date Sep 4, 2001
- Teradyne, Inc.
- Peter A. Reichert
- G11 - INFORMATION STORAGE
Information Patent Grant
Fast vector loading for automatic test equipment
- Patent number 5,737,512
- Issue date Apr 7, 1998
- Teradyne, Inc.
- David M. Proudfoot
- G01 - MEASURING TESTING
Information Patent Grant
Timing hazard detector accelerator
- Patent number 5,570,383
- Issue date Oct 29, 1996
- Teradyne, Inc.
- Benjamin J. Brown
- G01 - MEASURING TESTING
Information Patent Grant
Low cost timing generator for automatic test equipment operating at...
- Patent number 5,566,188
- Issue date Oct 15, 1996
- Teradyne, Inc.
- Bradford B. Robbins
- G01 - MEASURING TESTING
Information Patent Grant
High speed timing generator
- Patent number 5,321,702
- Issue date Jun 14, 1994
- Teradyne, Inc.
- Benjamin J. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed timing generator
- Patent number 5,321,700
- Issue date Jun 14, 1994
- Teradyne, Inc.
- Benjamin J. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed fail processor
- Patent number 5,280,486
- Issue date Jan 18, 1994
- Teradyne, Inc.
- Brian J. Arkin
- G01 - MEASURING TESTING
Information Patent Grant
High speed timing generator
- Patent number 5,270,582
- Issue date Dec 14, 1993
- Teradyne, Inc.
- Benjamin J. Brown
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CARRIER-BASED TEST SYSTEM
- Publication number 20200057093
- Publication date Feb 20, 2020
- Teradyne, Inc.
- Valquirio Nazare Carvalho
- G01 - MEASURING TESTING
Information Patent Application
METHOD OF AND SYSTEM FOR CALIBRATION OF INSPECTION SYSTEMS PRODUCIN...
- Publication number 20090218480
- Publication date Sep 3, 2009
- Govindarajan T. SRINIVASAN
- G01 - MEASURING TESTING
Information Patent Application
METHOD OF AND SYSTEM FOR OBTAINING LINEAR DATA FOR OBJECT SCANNED U...
- Publication number 20090218498
- Publication date Sep 3, 2009
- Peter A. Reichert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
X-RAY INSPECTION OF SOLDER REFLOW IN HIGH-DENSITY PRINTED CIRCUIT B...
- Publication number 20090080764
- Publication date Mar 26, 2009
- Teradyne, Inc.
- Govindarajan T. SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instrument with interface for synchronization in automatic test equ...
- Publication number 20080077350
- Publication date Mar 27, 2008
- Teradyne, Inc.
- Peter A. Reichert
- G01 - MEASURING TESTING
Information Patent Application
Multi-stream interface for parallel test processing
- Publication number 20070208985
- Publication date Sep 6, 2007
- Teradyne, Inc.
- Peter A. Reichert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automatic test system with synchronized instruments
- Publication number 20060123297
- Publication date Jun 8, 2006
- Teradyne, Inc.
- Peter A. Reichert
- G01 - MEASURING TESTING
Information Patent Application
Instrument with interface for synchronization in automatic test equ...
- Publication number 20060123296
- Publication date Jun 8, 2006
- Teradyne, Inc.
- Peter A. Reichert
- G01 - MEASURING TESTING
Information Patent Application
Multi-stage numeric counter oscillator
- Publication number 20050146360
- Publication date Jul 7, 2005
- Peter Reichert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock architecture for a frequency-based tester
- Publication number 20040205432
- Publication date Oct 14, 2004
- Robert Bruce Gage
- G01 - MEASURING TESTING

Peter Reichert

Person

Patents Grantslast 30 patents

System for testing devices inside of carriers

X-ray inspection of solder reflow in high-density printed circuit b...

Method of and system for calibration of inspection systems producin...

Instrument with interface for synchronization in automatic test equ...

Multi-stream interface for parallel test processing

Method of and system for obtaining linear data for object scanned u...

Automatic test system with synchronized instruments

Instrument with interface for synchronization in automatic test equ...

Multi-stage numeric counter oscillator

Clock architecture for a frequency-based tester

Low cost timing system for highly accurate multi-modal semiconducto...

Method and apparatus for testing integrated circuit chips that outp...

Pattern generator for a packet-based memory tester

Memory architecture for automatic test equipment using vector modul...

Fast vector loading for automatic test equipment

Timing hazard detector accelerator

Low cost timing generator for automatic test equipment operating at...

High speed timing generator

High speed timing generator

High speed fail processor

High speed timing generator

Patents Applicationslast 30 patents

CARRIER-BASED TEST SYSTEM

METHOD OF AND SYSTEM FOR CALIBRATION OF INSPECTION SYSTEMS PRODUCIN...

METHOD OF AND SYSTEM FOR OBTAINING LINEAR DATA FOR OBJECT SCANNED U...

X-RAY INSPECTION OF SOLDER REFLOW IN HIGH-DENSITY PRINTED CIRCUIT B...

Instrument with interface for synchronization in automatic test equ...

Multi-stream interface for parallel test processing

Automatic test system with synchronized instruments

Instrument with interface for synchronization in automatic test equ...

Multi-stage numeric counter oscillator

Clock architecture for a frequency-based tester