Rajesh Rengarajan

Person

Wappingers Falls, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dual trench isolation for CMOS with hybrid orientations
- Patent number 9,355,887
- Issue date May 31, 2016
- GLOBALFOUNDRIES Inc.
- Victor Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual trench isolation for CMOS with hybrid orientations
- Patent number 8,097,516
- Issue date Jan 17, 2012
- International Business Machines Corporation
- Victor Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enhancement of electron and hole mobilities in <110> Si under biaxi...
- Patent number 7,943,486
- Issue date May 17, 2011
- International Business Machines Corporation
- Victor Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and structure for reducing induced mechanical stresses
- Patent number 7,883,948
- Issue date Feb 8, 2011
- International Business Machines Corporation
- Brian J. Greene
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and structure for reducing induced mechanical stresses
- Patent number 7,572,689
- Issue date Aug 11, 2009
- International Business Machines Corporation
- Brian J. Greene
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a multi-workfunction gates for a CMOS circuit
- Patent number 7,473,607
- Issue date Jan 6, 2009
- International Business Machines Corporation
- Xiangdong Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enhancement of electron and hole mobilities in <110> Si under biaxi...
- Patent number 7,462,525
- Issue date Dec 9, 2008
- International Business Machines Corporation
- Victor Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enhancement of electron and hole mobilities in <110> Si under biaxi...
- Patent number 7,314,790
- Issue date Jan 1, 2008
- International Business Machines Corporation
- Victor Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enhancement of electron and hole mobilities in <110> Si under biaxi...
- Patent number 7,161,169
- Issue date Jan 9, 2007
- International Business Machines Corporation
- Victor Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Recessed shallow trench isolation structure nitride liner and metho...
- Patent number 6,960,818
- Issue date Nov 1, 2005
- Siemens Aktiengesellschaft
- Rajesh Rengarajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of reducing erosion of a nitride gate cap layer during react...
- Patent number 6,960,523
- Issue date Nov 1, 2005
- Infineon Technolgies AG
- Michael Maldei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicide proximity structures for CMOS device performance improvements
- Patent number 6,869,866
- Issue date Mar 22, 2005
- International Business Machines Corporation
- Dureseti Chidambarrao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of dual work function gate electrode
- Patent number 6,867,087
- Issue date Mar 15, 2005
- Infineon Technologies AG
- Kilho Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical MOSFET with horizontally graded channel doping
- Patent number 6,740,920
- Issue date May 25, 2004
- International Business Machines Corporation
- Dureseti Chidambarrao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method for dual work function logic devices in vertic...
- Patent number 6,635,526
- Issue date Oct 21, 2003
- Infineon Technologies AG
- Rajeev Malik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistors having independently adjustable parameters
- Patent number 6,501,131
- Issue date Dec 31, 2002
- International Business Machines Corporation
- Rama Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low bitline capacitance structure and method of making same
- Patent number 6,426,247
- Issue date Jul 30, 2002
- International Business Machines Corporation
- Ramachandra Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process of forming an ultra-shallow junction dopant layer having a...
- Patent number 6,387,782
- Issue date May 14, 2002
- International Business Machines Corporation
- Hiroyuki Akatsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating transistors
- Patent number 6,323,103
- Issue date Nov 27, 2001
- Siemens Aktiengesellschaft
- Rajesh Rengarajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for dual sidewall oxidation in high density, high performanc...
- Patent number 6,197,632
- Issue date Mar 6, 2001
- International Business Machines Corporation
- Gary B. Bronner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device performance by employing an improved method for forming halo...
- Patent number 6,194,278
- Issue date Feb 27, 2001
- Infineon Technologies North America Corp.
- Rajesh Rengarajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Deep pivot mask for enhanced buried-channel PFET performance and re...
- Patent number 6,127,215
- Issue date Oct 3, 2000
- International Business Machines Corp.
- Hans-Oliver Joachim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming electrical isolation for semiconductor devices
- Patent number 6,074,903
- Issue date Jun 13, 2000
- Siemens Aktiengesellschaft
- Rajesh Rengarajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Recessed shallow trench isolation structure nitride liner and metho...
- Patent number 5,940,717
- Issue date Aug 17, 1999
- Siemens Aktiengesellschaft
- Rajesh Rengarajan
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS
- Publication number 20120104511
- Publication date May 3, 2012
- International Business Machines Corporation
- Victor Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND STRUCTURE FOR REDUCING INDUCED MECHANICAL STRESSES
- Publication number 20090236640
- Publication date Sep 24, 2009
- International Business Machines Corporation
- Brian J. Greene
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND STRUCTURE FOR REDUCING INDUCED MECHANICAL STRESSES
- Publication number 20090121295
- Publication date May 14, 2009
- International Business Machines Corporation
- Brian J. Greene
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS
- Publication number 20080290379
- Publication date Nov 27, 2008
- International Business Machines Corporation
- Victor Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> Si UNDER BIAXI...
- Publication number 20080206958
- Publication date Aug 28, 2008
- International Business Machines Corporation
- Victor Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> Si UNDER BIAXI...
- Publication number 20080044987
- Publication date Feb 21, 2008
- International Business Machines Corporation
- Victor Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> Si UNDER BIAXI...
- Publication number 20080044966
- Publication date Feb 21, 2008
- International Business Machines Corporation
- Victor Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS
- Publication number 20080036028
- Publication date Feb 14, 2008
- International Business Machines Corporation
- Victor Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN 110 Si UNDER BIAXIAL...
- Publication number 20070099367
- Publication date May 3, 2007
- International Business Machines Corporation
- Victor Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual trench isolation for CMOS with hybrid orientations
- Publication number 20070040235
- Publication date Feb 22, 2007
- International Business Machines Corporation
- Victor Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multi-work function gates for CMOS circuit and method of manufacture
- Publication number 20070020865
- Publication date Jan 25, 2007
- International Business Machines Corporation
- Xiangdong Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Enhancement of electron and hole mobilities in <110> Si under biaxi...
- Publication number 20050145837
- Publication date Jul 7, 2005
- International Business Machines Corporation
- Victor Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SILICIDE PROXIMITY STRUCTURES FOR CMOS DEVICE PERFORMANCE IMPROVEMENTS
- Publication number 20050064687
- Publication date Mar 24, 2005
- International Business Machines Corporation
- Dureseti Chidambarrao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of reducing erosion of a nitride gate cap layer during react...
- Publication number 20040195607
- Publication date Oct 7, 2004
- Infineon Technologies North America Corp.
- Michael Maldei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Vertical MOSFET with horizontally graded channel doping
- Publication number 20030168687
- Publication date Sep 11, 2003
- International Business Machines Corporation
- Dureseti Chidambarrao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Formation of dual work function gate electrode
- Publication number 20030096471
- Publication date May 22, 2003
- Infineon Technologies North America Corp.
- Kilho Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Reducing threshold voltage roll-up/roll-off effect for MOSFETS
- Publication number 20020177264
- Publication date Nov 28, 2002
- International Business Machines Corporation
- Hiroyuki Akatsu
- H01 - BASIC ELECTRIC ELEMENTS

Rajesh Rengarajan

Person

Patents Grantslast 30 patents

Dual trench isolation for CMOS with hybrid orientations

Dual trench isolation for CMOS with hybrid orientations

Enhancement of electron and hole mobilities in <110> Si under biaxi...

Method and structure for reducing induced mechanical stresses

Method and structure for reducing induced mechanical stresses

Method of manufacturing a multi-workfunction gates for a CMOS circuit

Enhancement of electron and hole mobilities in <110> Si under biaxi...

Enhancement of electron and hole mobilities in <110> Si under biaxi...

Enhancement of electron and hole mobilities in <110> Si under biaxi...

Recessed shallow trench isolation structure nitride liner and metho...

Method of reducing erosion of a nitride gate cap layer during react...

Silicide proximity structures for CMOS device performance improvements

Formation of dual work function gate electrode

Vertical MOSFET with horizontally graded channel doping

Structure and method for dual work function logic devices in vertic...

Transistors having independently adjustable parameters

Low bitline capacitance structure and method of making same

Process of forming an ultra-shallow junction dopant layer having a...

Method for fabricating transistors

Method for dual sidewall oxidation in high density, high performanc...

Device performance by employing an improved method for forming halo...

Deep pivot mask for enhanced buried-channel PFET performance and re...

Method for forming electrical isolation for semiconductor devices

Recessed shallow trench isolation structure nitride liner and metho...

Patents Applicationslast 30 patents

DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS

METHOD AND STRUCTURE FOR REDUCING INDUCED MECHANICAL STRESSES

METHOD AND STRUCTURE FOR REDUCING INDUCED MECHANICAL STRESSES

DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS

ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> Si UNDER BIAXI...

ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> Si UNDER BIAXI...

ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> Si UNDER BIAXI...

DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS

ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN 110 Si UNDER BIAXIAL...

Dual trench isolation for CMOS with hybrid orientations

Multi-work function gates for CMOS circuit and method of manufacture

Enhancement of electron and hole mobilities in <110> Si under biaxi...

SILICIDE PROXIMITY STRUCTURES FOR CMOS DEVICE PERFORMANCE IMPROVEMENTS

Method of reducing erosion of a nitride gate cap layer during react...

Vertical MOSFET with horizontally graded channel doping

Formation of dual work function gate electrode

Reducing threshold voltage roll-up/roll-off effect for MOSFETS