Rama Divakaruni

Person

Ossining, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Conductive contacts in semiconductor on insulator substrate
- Patent number 11,177,285
- Issue date Nov 16, 2021
- ELPIS TECHNOLOGIES INC.
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Conductive contacts in semiconductor on insulator substrate
- Patent number 10,734,410
- Issue date Aug 4, 2020
- ELPIS TECHNOLOGIES INC.
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Conductive contacts in semiconductor on insulator substrate
- Patent number 9,685,535
- Issue date Jun 20, 2017
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fin isolation structures facilitating different fin isolation schemes
- Patent number 9,673,222
- Issue date Jun 6, 2017
- GLOBALFOUNDRIES Inc.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating self-aligned bipolar transistor having tapere...
- Patent number 7,615,457
- Issue date Nov 10, 2009
- International Business Machines Corporation
- Hiroyuki Akatsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High performance FET with elevated source/drain region
- Patent number 7,566,599
- Issue date Jul 28, 2009
- International Business Machines Corporation
- Rama Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a bipolar transistor having reduced collector...
- Patent number 7,462,547
- Issue date Dec 9, 2008
- International Business Machines Corporation
- Hiroyuki Akatsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method of self-aligned bipolar transistor having tape...
- Patent number 7,425,754
- Issue date Sep 16, 2008
- International Business Machines Corporation
- Hiroyuki Akatsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating semiconductor side wall fin
- Patent number 7,361,556
- Issue date Apr 22, 2008
- International Business Machines Corporation
- James W. Adkisson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating semiconductor side wall fin
- Patent number 7,265,417
- Issue date Sep 4, 2007
- International Business Machines Corporation
- James W. Adkisson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bipolar transistor having reduced collector-base capacitance
- Patent number 7,190,046
- Issue date Mar 13, 2007
- International Business Machines Corporation
- Hiroyuki Akatsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure of vertical strained silicon devices
- Patent number 7,170,126
- Issue date Jan 30, 2007
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating semiconductor side wall fin
- Patent number 7,163,864
- Issue date Jan 16, 2007
- International Business Machines Corporation
- James W. Adkisson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Double gate trench transistor
- Patent number 7,112,845
- Issue date Sep 26, 2006
- International Business Machines Corporation
- James W. Adkisson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density chip carrier with integrated passive devices
- Patent number 7,030,481
- Issue date Apr 18, 2006
- Internation Business Machines Corporation
- Michael Patrick Chudzik
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Nitrided STI liner oxide for reduced corner device impact on vertic...
- Patent number 6,998,666
- Issue date Feb 14, 2006
- International Business Machines Corporation
- Jochen Beintner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming collar structures in deep trench capacitors with thermally...
- Patent number 6,967,137
- Issue date Nov 22, 2005
- International Business Machines Corporation
- Michael P. Belyansky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
N-channel metal oxide semiconductor (NMOS) driver circuit and metho...
- Patent number 6,964,892
- Issue date Nov 15, 2005
- International Business Machines Corporation
- Lawrence A. Clevenger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density chip carrier with integrated passive devices
- Patent number 6,962,872
- Issue date Nov 8, 2005
- International Business Machines Corporation
- Michael Patrick Chudzik
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Pitcher-shaped active area for field effect transistor and method o...
- Patent number 6,960,514
- Issue date Nov 1, 2005
- International Business Machines Corporation
- Jochen Beintner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method of forming a bipolar transistor having a void...
- Patent number 6,940,149
- Issue date Sep 6, 2005
- International Business Machines Corporation
- Rama Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming TTO nitride liner for improved collar protection...
- Patent number 6,897,107
- Issue date May 24, 2005
- International Business Machines Corporation
- Rama Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduced cap layer erosion for borderless contacts
- Patent number 6,890,815
- Issue date May 10, 2005
- Infineon Technologies AG
- Johnathan Faltermeier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned array contact for memory cells
- Patent number 6,870,211
- Issue date Mar 22, 2005
- International Business Machines Corporation
- Rama Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Filling high aspect ratio isolation structures with polysilazane ba...
- Patent number 6,869,860
- Issue date Mar 22, 2005
- International Business Machines Corporation
- Michael P. Belyansky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High performance FET with elevated source/drain region
- Patent number 6,864,540
- Issue date Mar 8, 2005
- International Business Machines Corp.
- Rama Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High on-current device for high performance embedded DRAM (eDRAM) a...
- Patent number 6,821,857
- Issue date Nov 23, 2004
- International Business Machines Corporation
- Babar A. Khan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
TTO nitride liner for improved collar protection and TTO reliability
- Patent number 6,809,368
- Issue date Oct 26, 2004
- International Business Machines Corporation
- Rama Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integration scheme for enhancing capacitance of trench capacitors
- Patent number 6,806,138
- Issue date Oct 19, 2004
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and methods for process integration in vertical DRAM cell...
- Patent number 6,790,739
- Issue date Sep 14, 2004
- International Business Machines Corporation
- Rajeev Malik
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
CONDUCTIVE CONTACTS IN SEMICONDUCTOR ON INSULATOR SUBSTRATE
- Publication number 20200058677
- Publication date Feb 20, 2020
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONDUCTIVE CONTACTS IN SEMICONDUCTOR ON INSULATOR SUBSTRATE
- Publication number 20180076220
- Publication date Mar 15, 2018
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIN ISOLATION STRUCTURES FACILITATING DIFFERENT FIN ISOLATION SCHEMES
- Publication number 20160260742
- Publication date Sep 8, 2016
- GLOBALFOUNDRIES INC.
- Ajey Poovannummoottil JACOB
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATION SCHEME FOR MULTIPLE METAL GATE WORK FUNCTION STRUCTURES
- Publication number 20090108356
- Publication date Apr 30, 2009
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of fabricating self-aligned bipolar transistor having tapere...
- Publication number 20080318373
- Publication date Dec 25, 2008
- International Business Machines Corporation
- Hiroyuki Akatsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Fabrication of bipolar transistor having reduced collector-base cap...
- Publication number 20070096259
- Publication date May 3, 2007
- Hiroyuki Akatsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of fabricating semiconductor side wall fin
- Publication number 20070026617
- Publication date Feb 1, 2007
- James W. Adkisson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High performance FET with elevated source/drain region
- Publication number 20050260801
- Publication date Nov 24, 2005
- Rama Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD OF MAKING A BIPOLAR TRANSISTOR HAVING REDUCED...
- Publication number 20050212087
- Publication date Sep 29, 2005
- International Business Machines Corporation
- Hiroyuki Akatsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD OF FORMING A BIPOLAR TRANSISTOR HAVING A VOID...
- Publication number 20050199907
- Publication date Sep 15, 2005
- International Business Machines Corporation
- Rama Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD OF SELF-ALIGNED BIPOLAR TRANSISTOR HAVING TAPE...
- Publication number 20050184359
- Publication date Aug 25, 2005
- International Business Machines Corporation
- Hiroyuki Akatsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Filling high aspect ratio isolation structures with polysilazane ba...
- Publication number 20050179112
- Publication date Aug 18, 2005
- International Business Machines Corporation
- Michael P. Belyansky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NITRIDED STI LINER OXIDE FOR REDUCED CORNER DEVICE IMPACT ON VERTIC...
- Publication number 20050151181
- Publication date Jul 14, 2005
- International Business Machines Corporation
- Jochen Beintner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED ARRAY CONTACT FOR MEMORY CELLS
- Publication number 20050077562
- Publication date Apr 14, 2005
- International Business Machines Corporation
- Rama Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND STRUCTURE OF VERTICAL STRAINED SILICON DEVICES
- Publication number 20050059214
- Publication date Mar 17, 2005
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCED CAP LAYER EROSION FOR BORDERLESS CONTACTS
- Publication number 20050051839
- Publication date Mar 10, 2005
- Johnathan Faltermeier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BULK CONTACT MASK PROCESS
- Publication number 20050054158
- Publication date Mar 10, 2005
- International Business Machines Corporation
- Rama Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High density chip carrier with integrated passive devices
- Publication number 20050023664
- Publication date Feb 3, 2005
- Michael Patrick Chudzik
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
FORMING COLLAR STRUCTURES IN DEEP TRENCH CAPACITORS WITH THERMALLY...
- Publication number 20050009267
- Publication date Jan 13, 2005
- International Business Machines Corporation
- Michael P. Belyansky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of fabricating semiconductor side wall fin
- Publication number 20050001216
- Publication date Jan 6, 2005
- James W. Adkisson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH ON-CURRENT DEVICE FOR HIGH PERFORMANCE EMBEDDED DRAM (EDRAM) A...
- Publication number 20040251512
- Publication date Dec 16, 2004
- Babar A. Khan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FILLING HIGH ASPECT RATIO ISOLATION STRUCTURES WITH POLYSILAZANE BA...
- Publication number 20040248374
- Publication date Dec 9, 2004
- International Business Machines Corporation
- Michael P. Belyansky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Pitcher-shaped active area for field effect transistor and method o...
- Publication number 20040173858
- Publication date Sep 9, 2004
- Jochen Beintner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TTO nitride liner for improved collar protection and TTO reliability
- Publication number 20040155275
- Publication date Aug 12, 2004
- International Business Machines Corporation
- Rama Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High density chip carrier with integrated passive devices
- Publication number 20040108587
- Publication date Jun 10, 2004
- Michael Patrick Chudzik
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
TTO nitride liner for improved collar protection and TTO reliability
- Publication number 20040106258
- Publication date Jun 3, 2004
- International Business Machines Corporation
- Rama Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHODS FOR PROCESS INTEGRATION IN VERTICAL DRAM CELL...
- Publication number 20030186502
- Publication date Oct 2, 2003
- International Business Machines Corporation
- Rajeev Malik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DRAM array bit contact with relaxed pitch pattern
- Publication number 20030116784
- Publication date Jun 26, 2003
- International Business Machines Corporation
- Rama Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structure and methods for process integration in vertical DRAM cell...
- Publication number 20030003653
- Publication date Jan 2, 2003
- International Business Machines Corporation
- Rajeev Malik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TTO nitride liner for improved collar protection and TTO reliability
- Publication number 20020149047
- Publication date Oct 17, 2002
- International Business Machines Coporation
- Rama Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS

Rama Divakaruni

Person

Patents Grantslast 30 patents

Conductive contacts in semiconductor on insulator substrate

Conductive contacts in semiconductor on insulator substrate

Conductive contacts in semiconductor on insulator substrate

Fin isolation structures facilitating different fin isolation schemes

Method of fabricating self-aligned bipolar transistor having tapere...

High performance FET with elevated source/drain region

Method of fabricating a bipolar transistor having reduced collector...

Structure and method of self-aligned bipolar transistor having tape...

Method of fabricating semiconductor side wall fin

Method of fabricating semiconductor side wall fin

Bipolar transistor having reduced collector-base capacitance

Structure of vertical strained silicon devices

Method of fabricating semiconductor side wall fin

Double gate trench transistor

High density chip carrier with integrated passive devices

Nitrided STI liner oxide for reduced corner device impact on vertic...

Forming collar structures in deep trench capacitors with thermally...

N-channel metal oxide semiconductor (NMOS) driver circuit and metho...

High density chip carrier with integrated passive devices

Pitcher-shaped active area for field effect transistor and method o...

Structure and method of forming a bipolar transistor having a void...

Method for forming TTO nitride liner for improved collar protection...

Reduced cap layer erosion for borderless contacts

Self-aligned array contact for memory cells

Filling high aspect ratio isolation structures with polysilazane ba...

High performance FET with elevated source/drain region

High on-current device for high performance embedded DRAM (eDRAM) a...

TTO nitride liner for improved collar protection and TTO reliability

Integration scheme for enhancing capacitance of trench capacitors

Structure and methods for process integration in vertical DRAM cell...

Patents Applicationslast 30 patents

CONDUCTIVE CONTACTS IN SEMICONDUCTOR ON INSULATOR SUBSTRATE

CONDUCTIVE CONTACTS IN SEMICONDUCTOR ON INSULATOR SUBSTRATE

FIN ISOLATION STRUCTURES FACILITATING DIFFERENT FIN ISOLATION SCHEMES

INTEGRATION SCHEME FOR MULTIPLE METAL GATE WORK FUNCTION STRUCTURES

Method of fabricating self-aligned bipolar transistor having tapere...

Fabrication of bipolar transistor having reduced collector-base cap...

Method of fabricating semiconductor side wall fin

High performance FET with elevated source/drain region

STRUCTURE AND METHOD OF MAKING A BIPOLAR TRANSISTOR HAVING REDUCED...

STRUCTURE AND METHOD OF FORMING A BIPOLAR TRANSISTOR HAVING A VOID...

STRUCTURE AND METHOD OF SELF-ALIGNED BIPOLAR TRANSISTOR HAVING TAPE...

Filling high aspect ratio isolation structures with polysilazane ba...

NITRIDED STI LINER OXIDE FOR REDUCED CORNER DEVICE IMPACT ON VERTIC...

SELF-ALIGNED ARRAY CONTACT FOR MEMORY CELLS

METHOD AND STRUCTURE OF VERTICAL STRAINED SILICON DEVICES

REDUCED CAP LAYER EROSION FOR BORDERLESS CONTACTS

BULK CONTACT MASK PROCESS

High density chip carrier with integrated passive devices

FORMING COLLAR STRUCTURES IN DEEP TRENCH CAPACITORS WITH THERMALLY...

Method of fabricating semiconductor side wall fin

HIGH ON-CURRENT DEVICE FOR HIGH PERFORMANCE EMBEDDED DRAM (EDRAM) A...

FILLING HIGH ASPECT RATIO ISOLATION STRUCTURES WITH POLYSILAZANE BA...

Pitcher-shaped active area for field effect transistor and method o...

TTO nitride liner for improved collar protection and TTO reliability

High density chip carrier with integrated passive devices

TTO nitride liner for improved collar protection and TTO reliability

STRUCTURE AND METHODS FOR PROCESS INTEGRATION IN VERTICAL DRAM CELL...

DRAM array bit contact with relaxed pitch pattern

Structure and methods for process integration in vertical DRAM cell...

TTO nitride liner for improved collar protection and TTO reliability