Randy M. Bonella

Person

Cypress, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for high reliability data storage and retrieva...
- Patent number 7,941,592
- Issue date May 10, 2011
- Randy M. Bonella
- G11 - INFORMATION STORAGE
Information Patent Grant
Advanced dynamic disk memory module
- Patent number 7,681,004
- Issue date Mar 16, 2010
- ADDMM, LLC
- Randy M. Bonella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffering and interleaving data transfer between a chipset and memo...
- Patent number 7,249,232
- Issue date Jul 24, 2007
- Intel Corporation
- John B. Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual-port buffer-to-memory interface
- Patent number 7,024,518
- Issue date Apr 4, 2006
- Intel Corporation
- John B. Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory module and memory component built-in self test
- Patent number 6,928,593
- Issue date Aug 9, 2005
- Intel Corporation
- John Halbert
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital system of adjusting delays on circuit boards
- Patent number 6,928,571
- Issue date Aug 9, 2005
- Intel Corporation
- Randy M. Bonella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffering data transfer between a chipset and memory modules
- Patent number 6,820,163
- Issue date Nov 16, 2004
- Intel Corporation
- James A. McCall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory module having buffer for isolating stacked memory devices
- Patent number 6,747,887
- Issue date Jun 8, 2004
- Intel Corporation
- John B. Halbert
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual-port buffer-to-memory interface
- Patent number 6,742,098
- Issue date May 25, 2004
- Intel Corporation
- John B. Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffering and interleaving data transfer between a chipset and memo...
- Patent number 6,697,888
- Issue date Feb 24, 2004
- Intel Corporation
- John B. Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tier point-to-point ring memory interface
- Patent number 6,658,509
- Issue date Dec 2, 2003
- Intel Corporation
- Randy M. Bonella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory module employing a junction circuit for point-to-point conne...
- Patent number 6,625,687
- Issue date Sep 23, 2003
- Intel Corporation
- John B. Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing multiple memory buses on a me...
- Patent number 6,587,912
- Issue date Jul 1, 2003
- Intel Corporation
- Michael W. Leddige
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffer to multiply memory interface
- Patent number 6,553,450
- Issue date Apr 22, 2003
- Intel Corporation
- Jim M. Dodd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for providing reliable transmission in a buffered...
- Patent number 6,530,006
- Issue date Mar 4, 2003
- Intel Corporation
- James M. Dodd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tier point-to-point buffered memory interface
- Patent number 6,493,250
- Issue date Dec 10, 2002
- Intel Corporation
- John B. Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory module having buffer for isolating stacked memory devices
- Patent number 6,487,102
- Issue date Nov 26, 2002
- Intel Corporation
- John B. Halbert
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for implementing multiple memory buses on a memory module
- Patent number 6,477,614
- Issue date Nov 5, 2002
- Intel Corporation
- Michael W. Leddige
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory interface having source-synchronous command/address signaling
- Patent number 6,449,213
- Issue date Sep 10, 2002
- Intel Corporation
- James M. Dodd
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for retrieving data from a data storage device
- Patent number 6,397,291
- Issue date May 28, 2002
- Intel Corporation
- Randy M. Bonella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-terminated driver to prevent signal reflections of transmissio...
- Patent number 6,369,605
- Issue date Apr 9, 2002
- Intel Corporation
- Randy Bonella
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus for implementing a buffered daisy chain connection betwee...
- Patent number 6,317,352
- Issue date Nov 13, 2001
- Intel Corporation
- John B. Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for retrieving data from a data storage device
- Patent number 6,192,459
- Issue date Feb 20, 2001
- Intel Corporation
- Randy M. Bonella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Internally controlled signal system for controlling the operation o...
- Patent number 5,818,794
- Issue date Oct 6, 1998
- Intel Corporation
- Randy M. Bonella
- G11 - INFORMATION STORAGE
Information Patent Grant
Bus master arbitration circuitry having improved prioritization
- Patent number 5,797,020
- Issue date Aug 18, 1998
- Compaq Computer Corporation
- Randy M. Bonella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for selectively preventing a microprocessor from posting wr...
- Patent number 5,790,869
- Issue date Aug 4, 1998
- Compaq Computer Corporation
- Maria L. Melo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for selectively preventing a microprocessor from posting wr...
- Patent number 5,625,824
- Issue date Apr 29, 1997
- Compaq Computer Corporation
- Maria L. Melo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fully pipelined and highly concurrent memory controller
- Patent number 5,537,555
- Issue date Jul 16, 1996
- Compaq Computer Corporation
- John A. Landry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus master arbitration circuitry having improved prioritization
- Patent number 5,471,590
- Issue date Nov 28, 1995
- Compaq Computer Corp.
- Maria L. Melo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache snoop latency prevention apparatus
- Patent number 5,446,863
- Issue date Aug 29, 1995
- Compaq Computer Corporation
- Jeffrey C. Stevens
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Advanced Dynamic Disk Memory Module
- Publication number 20100223422
- Publication date Sep 2, 2010
- Randy M. Bonella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for high reliability data storage and retrieva...
- Publication number 20100042772
- Publication date Feb 18, 2010
- ADDMM, LLC
- Randy M. Bonella
- G11 - INFORMATION STORAGE
Information Patent Application
Advanced dynamic disk memory module special operations
- Publication number 20070136523
- Publication date Jun 14, 2007
- Randy M. Bonella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Advanced dynamic disk memory module
- Publication number 20070079065
- Publication date Apr 5, 2007
- Randy M. Bonella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Buffering and interleaving data transfer between a chipset and memo...
- Publication number 20040188704
- Publication date Sep 30, 2004
- Intel Corporation, a Delaware corporation
- John B. Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory module having buffer for isolating stacked memory devices
- Publication number 20030035312
- Publication date Feb 20, 2003
- Intel Corporation
- John B. Halbert
- G11 - INFORMATION STORAGE
Information Patent Application
Dual-port buffer-to-memory interface
- Publication number 20020112119
- Publication date Aug 15, 2002
- Intel Corporation
- John B. Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TIER POINT-TO-POINT BUFFERED MEMORY INTERFACE
- Publication number 20020084458
- Publication date Jul 4, 2002
- John B. Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IMPLEMENTING MULTIPLE MEMORY BUSES ON A ME...
- Publication number 20020038405
- Publication date Mar 28, 2002
- MICHAEL W. LEDDIGE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for retrieving data from a data storage device
- Publication number 20010011317
- Publication date Aug 2, 2001
- Randy M. Bonella
- G06 - COMPUTING CALCULATING COUNTING

Randy M. Bonella

Person

Patents Grantslast 30 patents

Method and apparatus for high reliability data storage and retrieva...

Advanced dynamic disk memory module

Buffering and interleaving data transfer between a chipset and memo...

Dual-port buffer-to-memory interface

Memory module and memory component built-in self test

Digital system of adjusting delays on circuit boards

Buffering data transfer between a chipset and memory modules

Memory module having buffer for isolating stacked memory devices

Dual-port buffer-to-memory interface

Buffering and interleaving data transfer between a chipset and memo...

Multi-tier point-to-point ring memory interface

Memory module employing a junction circuit for point-to-point conne...

Method and apparatus for implementing multiple memory buses on a me...

Buffer to multiply memory interface

System and method for providing reliable transmission in a buffered...

Multi-tier point-to-point buffered memory interface

Memory module having buffer for isolating stacked memory devices

Method for implementing multiple memory buses on a memory module

Memory interface having source-synchronous command/address signaling

Method and apparatus for retrieving data from a data storage device

Self-terminated driver to prevent signal reflections of transmissio...

Apparatus for implementing a buffered daisy chain connection betwee...

Method and apparatus for retrieving data from a data storage device

Internally controlled signal system for controlling the operation o...

Bus master arbitration circuitry having improved prioritization

Circuit for selectively preventing a microprocessor from posting wr...

Circuit for selectively preventing a microprocessor from posting wr...

Fully pipelined and highly concurrent memory controller

Bus master arbitration circuitry having improved prioritization

Cache snoop latency prevention apparatus

Patents Applicationslast 30 patents

Advanced Dynamic Disk Memory Module

Method and apparatus for high reliability data storage and retrieva...

Advanced dynamic disk memory module special operations

Advanced dynamic disk memory module

Buffering and interleaving data transfer between a chipset and memo...

Memory module having buffer for isolating stacked memory devices

Dual-port buffer-to-memory interface

MULTI-TIER POINT-TO-POINT BUFFERED MEMORY INTERFACE

METHOD AND APPARATUS FOR IMPLEMENTING MULTIPLE MEMORY BUSES ON A ME...

Method and apparatus for retrieving data from a data storage device