Richard C. Foss

Person

Calabogie, CA

People

Patents Grantslast 30 patents

Information Patent Grant
Delay locked loop implementation in a synchronous dynamic random ac...
- Patent number 8,638,638
- Issue date Jan 28, 2014
- MOSAID Technologies Incorporated
- Richard C. Foss
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay locked loop implementation in a synchronous dynamic random ac...
- Patent number 8,369,182
- Issue date Feb 5, 2013
- Mosaid Technologies Incorporated
- Richard C. Foss
- G11 - INFORMATION STORAGE
Information Patent Grant
Error correction scheme for memory
- Patent number 7,636,880
- Issue date Dec 22, 2009
- MOSAID Technologies Incorporated
- Richard Foss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay locked loop implementation in a synchronous dynamic random ac...
- Patent number 7,599,246
- Issue date Oct 6, 2009
- MOSAID Technologies, Inc.
- Richard C. Foss
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic random access memory using imperfect isolating transistors
- Patent number RE40552
- Issue date Oct 28, 2008
- Mosaid Technologies, Inc.
- Richard C. Foss
- 365 - Static information storage and retrieval
Information Patent Grant
Method and circuit for error correction in CAM cells
- Patent number 7,350,137
- Issue date Mar 25, 2008
- Mosaid Technologies Incorporated
- Richard Foss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error correction scheme for memory
- Patent number 7,266,747
- Issue date Sep 4, 2007
- Mosaid Technologies Incorporated
- Richard Foss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and circuit for error correction in CAM cells
- Patent number 7,010,741
- Issue date Mar 7, 2006
- Mosaid Technologies
- Richard Foss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay locked loop implementation in a synchronous dynamic random ac...
- Patent number 6,992,950
- Issue date Jan 31, 2006
- Mosaid Technologies Incorporated
- Richard C. Foss
- G11 - INFORMATION STORAGE
Information Patent Grant
Delayed locked loop implementation in a synchronous dynamic random...
- Patent number 6,657,919
- Issue date Dec 2, 2003
- Mosaid Technologies Incorporated
- Richard C. Foss
- G11 - INFORMATION STORAGE
Information Patent Grant
Delayed locked loop implementation in a synchronous dynamic random...
- Patent number 6,657,918
- Issue date Dec 2, 2003
- Mosaid Technologies Incorporated
- Richard C. Foss
- G11 - INFORMATION STORAGE
Information Patent Grant
Boosted voltage supply
- Patent number 6,580,654
- Issue date Jun 17, 2003
- Mosaid Technologies, Inc.
- Richard C. Foss
- G11 - INFORMATION STORAGE
Information Patent Grant
Delayed locked loop implementation in a synchronous dynamic random...
- Patent number 6,314,052
- Issue date Nov 6, 2001
- Mosaid Technologies Incorporated
- Richard C. Foss
- G11 - INFORMATION STORAGE
Information Patent Grant
Delayed locked loop implementation in a synchronous dynamic random...
- Patent number 6,205,083
- Issue date Mar 20, 2001
- Mosaid Technologies Incorporated
- Richard C. Foss
- G11 - INFORMATION STORAGE
Information Patent Grant
Delayed locked loop implementation in a synchronous dynamic random...
- Patent number 6,067,272
- Issue date May 23, 2000
- Mosaid Technologies Incorporated
- Richard C. Foss
- G11 - INFORMATION STORAGE
Information Patent Grant
Built in access time comparator
- Patent number 5,844,916
- Issue date Dec 1, 1998
- Mosaid Technologies Incorporated
- Richard C. Foss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay locked loop implementation in a synchronous dynamic random ac...
- Patent number 5,796,673
- Issue date Aug 18, 1998
- Mosaid Technologies Incorporated
- Richard C. Foss
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic memory row/column redundancy scheme
- Patent number 5,245,576
- Issue date Sep 14, 1993
- Richard C. Foss
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic memory bit line precharge scheme
- Patent number 5,233,560
- Issue date Aug 3, 1993
- Richard C. Foss
- G11 - INFORMATION STORAGE
Information Patent Grant
Folded bitline dynamic RAM with reduced shared supply voltages
- Patent number 5,093,808
- Issue date Mar 3, 1992
- Mosaid, Inc.
- Richard C. Foss
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory circuit with parallel and serial input and output
- Patent number 5,014,244
- Issue date May 7, 1991
- U.S. Philips Corp.
- Judocus A. M. Lammerts
- G11 - INFORMATION STORAGE
Information Patent Grant
Folded bitline dynamic ram with reduced shared supply voltages
- Patent number 4,980,862
- Issue date Dec 25, 1990
- Mosaid, Inc.
- Richard C. Foss
- G11 - INFORMATION STORAGE
Information Patent Grant
Output buffer having sequentially-switched output
- Patent number 4,789,796
- Issue date Dec 6, 1988
- U.S. Philips Corporation
- Richard C. Foss
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
CMOS input buffer circuit for TTL signals
- Patent number 4,786,830
- Issue date Nov 22, 1988
- U.S. Philips Corporation
- Richard C. Foss
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic logic circuits operating in a differential mode for array p...
- Patent number 4,367,420
- Issue date Jan 4, 1983
- Thompson Foss Incorporated
- Richard C. Foss
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Delay Locked Loop Implementation In A Synchronous Dynamic Random Ac...
- Publication number 20140104969
- Publication date Apr 17, 2014
- MOSAID TECHNOLOGIES INCORPORATED
- Richard C. Foss
- G11 - INFORMATION STORAGE
Information Patent Application
Delay Locked Loop Implementation In A Synchronous Dynamic Random Ac...
- Publication number 20130121096
- Publication date May 16, 2013
- MOSAID TECHNOLOGIES INCORPORATED
- Richard C. Foss
- G11 - INFORMATION STORAGE
Information Patent Application
Delay Locked Loop Implementation in a Synchronous Dynamic Random Ac...
- Publication number 20090316514
- Publication date Dec 24, 2009
- Richard C. Foss
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ERROR CORRECTION SCHEME FOR MEMORY
- Publication number 20070300100
- Publication date Dec 27, 2007
- MOSAID Technologies Incorporated
- Richard C. FOSS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and circuit for error correction in CAM cells
- Publication number 20060123327
- Publication date Jun 8, 2006
- MOSAID Technologies Incorporated
- Richard Foss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Delay locked loop implementation in a synchronous dynamic random ac...
- Publication number 20050265506
- Publication date Dec 1, 2005
- MOSAID Technologies, Inc.
- Richard C. Foss
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Delayed locked loop implementation in a synchronous dynamic random...
- Publication number 20040130962
- Publication date Jul 8, 2004
- MOSAID Technologies Incorporated
- Richard C. Foss
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Error correction scheme for memory
- Publication number 20040117723
- Publication date Jun 17, 2004
- Richard C. Foss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and circuit for error correction in CAM cells
- Publication number 20040083421
- Publication date Apr 29, 2004
- Richard Foss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Delayed locked loop implementation in a synchronous dynamic random...
- Publication number 20030107944
- Publication date Jun 12, 2003
- MOSAID Technologies Incorporated
- Richard C. Foss
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Delayed locked loop implementation in a synchronous dynamic random...
- Publication number 20030090952
- Publication date May 15, 2003
- Richard C. Foss
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Boosted voltage supply
- Publication number 20020075706
- Publication date Jun 20, 2002
- MOSAID Technologies Incorporated
- Richard C. Foss
- G05 - CONTROLLING REGULATING
Information Patent Application
Delayed locked loop implementation in a synchronous dynamic random...
- Publication number 20020075747
- Publication date Jun 20, 2002
- MOSAID Technologies Incorporated
- Richard C. Foss
- G11 - INFORMATION STORAGE
Information Patent Application
Delayed locked loop implementation in a synchronous dynamic random...
- Publication number 20010001601
- Publication date May 24, 2001
- MOSAID Technologies Incorporated
- Richard C. Foss
- G11 - INFORMATION STORAGE

Richard C. Foss

Person

Patents Grantslast 30 patents

Delay locked loop implementation in a synchronous dynamic random ac...

Delay locked loop implementation in a synchronous dynamic random ac...

Error correction scheme for memory

Delay locked loop implementation in a synchronous dynamic random ac...

Dynamic random access memory using imperfect isolating transistors

Method and circuit for error correction in CAM cells

Error correction scheme for memory

Method and circuit for error correction in CAM cells

Delay locked loop implementation in a synchronous dynamic random ac...

Delayed locked loop implementation in a synchronous dynamic random...

Delayed locked loop implementation in a synchronous dynamic random...

Boosted voltage supply

Delayed locked loop implementation in a synchronous dynamic random...

Delayed locked loop implementation in a synchronous dynamic random...

Delayed locked loop implementation in a synchronous dynamic random...

Built in access time comparator

Delay locked loop implementation in a synchronous dynamic random ac...

Dynamic memory row/column redundancy scheme

Dynamic memory bit line precharge scheme

Folded bitline dynamic RAM with reduced shared supply voltages

Integrated memory circuit with parallel and serial input and output

Folded bitline dynamic ram with reduced shared supply voltages

Output buffer having sequentially-switched output

CMOS input buffer circuit for TTL signals

Dynamic logic circuits operating in a differential mode for array p...

Patents Applicationslast 30 patents

Delay Locked Loop Implementation In A Synchronous Dynamic Random Ac...

Delay Locked Loop Implementation In A Synchronous Dynamic Random Ac...

Delay Locked Loop Implementation in a Synchronous Dynamic Random Ac...

ERROR CORRECTION SCHEME FOR MEMORY

Method and circuit for error correction in CAM cells

Delay locked loop implementation in a synchronous dynamic random ac...

Delayed locked loop implementation in a synchronous dynamic random...

Error correction scheme for memory

Method and circuit for error correction in CAM cells

Delayed locked loop implementation in a synchronous dynamic random...

Delayed locked loop implementation in a synchronous dynamic random...

Boosted voltage supply

Delayed locked loop implementation in a synchronous dynamic random...

Delayed locked loop implementation in a synchronous dynamic random...