Claims
- 1. A synchronous memory comprising:a clock input signal; an adjustable delay line for generating a data output driving clock signal from the clock input signal; and a data output buffer enabled by the driving clock signal for outputting data to an output terminal, the data being output to the output terminal at the same time as or a minimum time following an edge of the clock input signal.
- 2. Synchronous memory as claimed in claim 1 herein the adjustable delay line is in a delay locked loop.
- 3. Synchronous memory as claimed in claim 2 wherein the delay locked loop further comprises a delay model circuit which uses similar elements as the circuit path taken by the clock input signal.
- 4. Synchronous memory as claimed in claim 2 wherein the adjustable delay line is a tapped delay line.
- 5. Synchronous memory as claimed in claim 4 wherein taps provide plural outputs of the delay line.
- 6. Synchronous memory as claimed in claim 1 wherein the adjustable delay line is adapted to be disabled as a clock source to the data output buffer.
- 7. Synchronous memory as claimed in claim 1 wherein the adjustable delay line is used only to enable the data output buffer.
- 8. A synchronous dynamic random access memory comprising:a clock input signal; a delay locked loop comprising an adjustable delay line for generating a data output driving clock signal from the clock input signal; and a data output buffer enabled by the driving clock signal for outputting data to an output terminal, the data being output to the output terminal at the same time as or a minimum time following an edge of the clock input signal.
- 9. A method of enabling synchronous memory data output comprising:delaying a clock input signal in an adjustable delay line to generate a data output driving clock signal; and enabling output data with the driving clock signal, the data being output to an output terminal at the same time as or a minimum time following an edge of the clock input signal.
- 10. A method of enabling synchronous memory data output as claimed in claim 9 wherein the adjustable delay line is in a delay locked loop.
- 11. A method of enabling synchronous memory data output as claimed in claim 10 wherein the delay locked loop further comprises a delay model circuit which uses similar elements as the circuit path taken by the clock input signal.
- 12. A method of enabling synchronous memory data output as claimed in claim 10 wherein the adjustable delay line is a tapped delay line.
- 13. A method of enabling synchronous memory data output as claimed in claim 12 wherein taps provide plural outputs of the delay line.
- 14. A method of enabling synchronous memory data output as claimed in claim 9 further comprising disabling the adjustable delay line as a clock source for enabling output data.
- 15. A method of enabling synchronous memory data output as claimed in claim 9 wherein the adjustable delay line is used only to enable output data.
- 16. A method of enabling synchronous random access memory data output comprising:delaying a clock input signal in an adjustable delay line of a delay locked loop to generate a data output driving clock signal; and enabling output data with the driving clock signal, the data being output to an output terminal at the same time as or a minimum time following an edge of the clock input signal.
- 17. A synchronous dynamic random access memory comprising:means for delaying a clock input signal in an adjustable delay line of a delay locked loop to generate a data output driving clock signal; and means for enabling output data with the driving clock signal, the data being output to an output terminal at the same time as or a minimum time following an edge of the clock input signal.
RELATED APPLICATIONS
This application is a Continuation of Application Ser. No. 10/279,217, filed Oct. 23, 2002, which is a Continuation of Application Ser. No. 09/977,088, filed Oct. 12, 2001, which is a Continuation of Application Ser. No. 09/761,274, filed Jan. 16, 2001, now U.S. Pat. No. 6,314,052, which is a Continuation of Application Ser. No. 09/392,088 filed Sep. 8, 1999, now U.S. Pat. No. 6,205,083 which is a Continuation of Application Ser. No. 08/996,095 filed Dec. 22, 1997, now U.S. Pat. No. 6,067,272, which is a Continuation of Application Ser. No. 08/319,042, filed Oct. 6, 1994, now U.S. Pat. No. 5,796,673. The entire teachings of the above applications are incorporated herein by reference.
US Referenced Citations (12)
Foreign Referenced Citations (1)
Number |
Date |
Country |
0214094 |
Aug 1990 |
JP |
Non-Patent Literature Citations (4)
Entry |
Nakamura, Kazuyuki, et al., “A 200-MHz Pipelined 16-Mb BiCMOS SRAM with PLL Proportional Self-Timing Generator,” IEEE Journal of Solid-State Circuits, vol. 29, No. 11, pp. 1317-1322 (Nov. 1994). |
Kushiyama, N., et al., “500 Mbyte/sec Data-Rate 512 Kbits x 9 DRAM Using a Novel I/O Interface,” 1992 Symposium on VLSI Circuits Digest of Technical Papers, pp. 66-67 (1992). |
Kushiyama, Natsuki, et al., “A 500-Megabyte/s Data-Rate 4.5M DRAM,” IEEE Journal of Solid-State Circuits, vol. 28, No. 4, pp. 490-498 (Apr. 1993). |
Nakamura, Kazuyuki, et al., “A 220MHz Pipelined 16Mb BiCMOS SRAM with PLL Proportional Self-Timing Generator,” IEEE International Solid-State Circuits Conference, Session 15, pp. 258-259, 200-201 & 312 (Feb. 18, 1994). |
Continuations (6)
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10/279217 |
Oct 2002 |
US |
Child |
10/348062 |
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Parent |
09/977088 |
Oct 2001 |
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10/279217 |
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US |
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09/761274 |
Jan 2001 |
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09/977088 |
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US |
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09/392088 |
Sep 1999 |
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09/761274 |
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Parent |
08/996095 |
Dec 1997 |
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09/392088 |
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08/319042 |
Oct 1994 |
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08/996095 |
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US |