Claims
- 1. A synchronous memory comprising:
a clock input signal; an adjustable delay line for generating a data output driving clock signal from the clock input signal; and a data output buffer enabled by the driving clock signal for outputting data to an output terminal, the data being output to the output terminal at the same time as or a minimum time following an edge of the clock input signal.
- 2. Synchronous memory as claimed in claim 1 herein the adjustable delay line is in a delay locked loop.
- 3. Synchronous memory as claimed in claim 2 wherein the delay locked loop further comprises a delay model circuit which uses similar elements as the real circuit path.
- 4. Synchronous memory as claimed in claim 2 wherein the adjustable delay line is a tapped delay line.
- 5. Synchronous memory as claimed in claim 4 wherein taps provide plural outputs of the delay line.
- 6. Synchronous memory as claimed in claim 1 wherein the adjustable delay line is adapted to be disabled as a clock source to the data output buffer.
- 7. Synchronous memory as claimed in claim 1 wherein the adjustable delay line is used only to enable the data output buffer.
- 8. A synchronous dynamic random access memory comprising:
a clock input signal; a delay locked loop comprising an adjustable delay line for generating a data output driving clock signal from the clock input signal; and a data output buffer enabled by the driving clock signal for outputting data to an output terminal, the data being output to the output terminal at the same time as or a minimum time following an edge of the clock input signal.
- 9. A method of enabling synchronous memory data output comprising:
delaying a clock input signal in an adjustable delay line to generate a data output driving clock signal; and enabling output data with the driving clock signal, the data being output to an output terminal at the same time as or a minimum time following an edge of the clock input signal.
- 10. A method of enabling synchronous memory data output as claimed in claim 9 wherein the adjustable delay line is in a delay locked loop.
- 11. A method of enabling synchronous memory data output as claimed in claim 10 wherein the delay locked loop further comprises a delay model circuit which uses similar elements as the real circuit path.
- 12. A method of enabling synchronous memory data output as claimed in claim 10 wherein the adjustable delay line is a tapped delay line.
- 13. A method of enabling synchronous memory data output as claimed in claim 12 wherein taps provide plural outputs of the delay line.
- 14. A method of enabling synchronous memory data output as claimed in claim 9 further comprising disabling the adjustable delay line as a clock source for enabling output data.
- 15. A method of enabling synchronous memory data output as claimed in claim 9 wherein the adjustable delay line is used only to enable output data.
- 16. A method of enabling synchronous random access memory data output comprising:
delaying a clock input signal in an adjustable delay line of a delay locked loop to generate a data output driving clock signal; and enabling output data with the driving clock signal, the data being output to an output terminal at the same time as or a minimum time following an edge of the clock input signal.
- 17. A synchronous dynamic random access memory comprising:
means for delaying a clock input signal in an adjustable delay line of a delay locked loop to generate a data output driving clock signal; and means for enabling output data with the driving clock signal, the data being output to an output terminal at the same time as or a minimum time following an edge of the clock input signal.
RELATED APPLICATIONS
[0001] This application is a Continuation of application Ser. No. 10/279,217, filed Oct. 23, 2002, which is a Continuation of application Ser. No. 09/977,088, filed Oct. 12, 2001, which is a Continuation of application Ser. No. 09/761,274, filed Jan. 16, 2001, now U.S. Pat. No. 6,314,052, which is a Continuation of application Ser. No. 09/392,088 filed Sep. 8, 1999, now U.S. Pat. No. 6,205,083 which is a Continuation of application Ser. No. 08/996,095 filed Dec. 22, 1997, now U.S. Pat. No. 6,067,272, which is a Continuation of application Ser. No. 08/319,042, filed Oct. 6, 1994, now U.S. Pat. No. 5,796,673. The entire teachings of the above applications are incorporated herein by reference.
Continuations (6)
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Number |
Date |
Country |
Parent |
10279217 |
Oct 2002 |
US |
Child |
10348062 |
Jan 2003 |
US |
Parent |
09977088 |
Oct 2001 |
US |
Child |
10279217 |
Oct 2002 |
US |
Parent |
09761274 |
Jan 2001 |
US |
Child |
09977088 |
Oct 2001 |
US |
Parent |
09392088 |
Sep 1999 |
US |
Child |
09761274 |
Jan 2001 |
US |
Parent |
08996095 |
Dec 1997 |
US |
Child |
09392088 |
Sep 1999 |
US |
Parent |
08319042 |
Oct 1994 |
US |
Child |
08996095 |
Dec 1997 |
US |