Richard Stephen Roy

Person

Danville, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Sense amplifiers
- Patent number 7,859,929
- Issue date Dec 28, 2010
- T-RAM Semiconductor, Inc.
- Richard Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
State maintenance pulsing for a memory device
- Patent number 7,379,381
- Issue date May 27, 2008
- T-RAM Semiconductor, Inc.
- Richard Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Bitline shielding for thyristor-based memory
- Patent number 7,319,622
- Issue date Jan 15, 2008
- T-RAM Semiconductor, Inc.
- Richard Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for providing a redundant memory array in a semic...
- Patent number 7,158,425
- Issue date Jan 2, 2007
- Mosaic Systems, Inc.
- Chao-Wu Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable I/O buffer
- Patent number 6,937,055
- Issue date Aug 30, 2005
- Mosaic Systems, Inc.
- Richard Stephen Roy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Simultaneous access and cache loading in a hierarchically organized...
- Patent number 6,886,078
- Issue date Apr 26, 2005
- Virage Logic Corp.
- Richard S. Roy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed interface for parallel testing of multiple devices usin...
- Patent number 6,678,850
- Issue date Jan 13, 2004
- FormFactor, Inc.
- Richard S. Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Electronic component overlapping dice of unsingulated semiconductor...
- Patent number 6,664,628
- Issue date Dec 16, 2003
- FormFactor, Inc.
- Igor Y. Khandros
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Efficient parallel testing of semiconductor devices using a known g...
- Patent number 6,559,671
- Issue date May 6, 2003
- FormFactor, Inc.
- Charles A. Miller
- G01 - MEASURING TESTING
Information Patent Grant
Distributed interface for parallel testing of multiple devices usin...
- Patent number 6,499,121
- Issue date Dec 24, 2002
- FormFactor, Inc.
- Richard S. Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Parallel testing of integrated circuit devices using cross-DUT and...
- Patent number 6,480,978
- Issue date Nov 12, 2002
- FormFactor, Inc.
- Richard S. Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Compilable block clear mechanism on per I/O basis for high-speed me...
- Patent number 6,466,504
- Issue date Oct 15, 2002
- Virage Logic Corp.
- Richard S. Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Efficient parallel testing of integrated circuit devices using a kn...
- Patent number 6,452,411
- Issue date Sep 17, 2002
- FormFactor, Inc.
- Charles A. Miller
- G01 - MEASURING TESTING
Information Patent Grant
Fast read/write cycle memory device having a self-timed read/write...
- Patent number 6,392,957
- Issue date May 21, 2002
- Virage Logic Corporation
- Alexander Shubat
- G11 - INFORMATION STORAGE
Information Patent Grant
Reduced latency row selection circuit and method
- Patent number 6,356,503
- Issue date Mar 12, 2002
- Virage Logic Corp.
- Richard Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Interconnect assemblies and methods including ancillary electronic...
- Patent number 6,330,164
- Issue date Dec 11, 2001
- FormFactor, Inc.
- Igor Y. Khandros
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Hierarchical sense amp and write driver circuitry for compilable me...
- Patent number 6,292,427
- Issue date Sep 18, 2001
- Virage Logic Corp.
- Richard S. Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-timed clock circuitry in a multi-bank memory instance using a...
- Patent number 6,282,131
- Issue date Aug 28, 2001
- Virage Logic Corp.
- Richard S. Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Fast full signal differential output path circuit for high-speed me...
- Patent number 6,249,471
- Issue date Jun 19, 2001
- Virage Logic Corp.
- Richard S. Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Centrally decoded divided wordline (DWL) memory architecture
- Patent number 6,236,618
- Issue date May 22, 2001
- Virage Logic Corp.
- Richard Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Independent multichannel memory architecture
- Patent number 6,125,421
- Issue date Sep 26, 2000
- Hitachi Micro Systems, Inc.
- Richard Stephen Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Independent and cooperative multichannel memory architecture for us...
- Patent number 6,065,092
- Issue date May 16, 2000
- Hitachi Micro Systems, Inc.
- Richard Stephen Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-directional small signal transceiver/repeater
- Patent number 5,808,487
- Issue date Sep 15, 1998
- Hitachi Micro Systems, Inc.
- Richard Stephen Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase linking of output clock with master clock in memory architecture
- Patent number 5,805,873
- Issue date Sep 8, 1998
- Hitachi Micro Systems, Inc.
- Richard Stephen Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for post-fabrication ascertaining and providin...
- Patent number 5,539,349
- Issue date Jul 23, 1996
- Hitachi Microsystems, Inc.
- Richard S. Roy
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
System and method for providing a redundant memory array in a semic...
- Publication number 20050024912
- Publication date Feb 3, 2005
- Mosaic Systems, Inc.
- Chao-Wu Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Programmable I/O buffer
- Publication number 20040119497
- Publication date Jun 24, 2004
- Richard Stephen Roy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Distributed interface for parallel testing of multiple devices usin...
- Publication number 20030126534
- Publication date Jul 3, 2003
- FormFactor, Inc.
- Richard S. Roy
- G01 - MEASURING TESTING
Information Patent Application
Efficient parallel testing of semiconductor devices using a known g...
- Publication number 20020175697
- Publication date Nov 28, 2002
- FormFactor, Inc.
- Charles A. Miller
- G01 - MEASURING TESTING
Information Patent Application
Electronic component overlapping dice of unsingulated semiconductor...
- Publication number 20020074653
- Publication date Jun 20, 2002
- FormFactor, Inc.
- Igor Y. Khandros
- H01 - BASIC ELECTRIC ELEMENTS

Richard Stephen Roy

Person

Patents Grantslast 30 patents

Sense amplifiers

State maintenance pulsing for a memory device

Bitline shielding for thyristor-based memory

System and method for providing a redundant memory array in a semic...

Programmable I/O buffer

Simultaneous access and cache loading in a hierarchically organized...

Distributed interface for parallel testing of multiple devices usin...

Electronic component overlapping dice of unsingulated semiconductor...

Efficient parallel testing of semiconductor devices using a known g...

Distributed interface for parallel testing of multiple devices usin...

Parallel testing of integrated circuit devices using cross-DUT and...

Compilable block clear mechanism on per I/O basis for high-speed me...

Efficient parallel testing of integrated circuit devices using a kn...

Fast read/write cycle memory device having a self-timed read/write...

Reduced latency row selection circuit and method

Interconnect assemblies and methods including ancillary electronic...

Hierarchical sense amp and write driver circuitry for compilable me...

Self-timed clock circuitry in a multi-bank memory instance using a...

Fast full signal differential output path circuit for high-speed me...

Centrally decoded divided wordline (DWL) memory architecture

Independent multichannel memory architecture

Independent and cooperative multichannel memory architecture for us...

Multi-directional small signal transceiver/repeater

Phase linking of output clock with master clock in memory architecture

Method and apparatus for post-fabrication ascertaining and providin...

Patents Applicationslast 30 patents

System and method for providing a redundant memory array in a semic...

Programmable I/O buffer

Distributed interface for parallel testing of multiple devices usin...

Efficient parallel testing of semiconductor devices using a known g...

Electronic component overlapping dice of unsingulated semiconductor...