Claims
- 1. A system comprising:
a tester having at least one set of tester input/output (I/O) lines, the tester providing data values for testing a single device under test (DUT) on each set of tester I/O lines; and a contact assembly comprising a plurality of elements for contacting a plurality of signal locations of two or more DUTs, and circuitry having an input coupled to the at least one set of tester I/O lines and an output coupled to the probes, the circuitry providing said data values at the output and performing a comparison using data values read from the DUTs to determine errors, if any, in said DUTs, and providing error values indicative of said errors.
- 2. The system of claim 1 wherein the DUTs are memory devices and wherein the error values represent a difference between a data value read from the memory devices and an expected data value received by the circuitry from the tester for a predefined address.
- 3a. The system of claim 2 wherein the circuitry provides an error bit on each of said I/O lines, each error bit representing the error status of a separate DUT.
- 3b. The system of claim 1 wherein each of the DUTs is part of a packaged semiconductor IC device being tested.
- 4. A contact assembly comprising:
a plurality of probes for contacting a plurality of signal locations of two or more devices under test (DUTs); and first circuitry having an input coupled to a channel of a semiconductor tester, and an output coupled to the probes, the output driving data values into the DUTs in response to receiving said data values at the input, the circuitry sensing data values from the DUTs and providing error information in response to performing a comparison using data values.
- 5. The contact assembly of claim 4 further comprising:
second circuitry being substantially the same as the first circuitry and coupled to the channel and the probes, the first circuitry driving data values into a first set of the DUTs and the second circuitry driving data values into a second set of the DUTs separate from the first set.
- 6. The contact assembly of claim 5 wherein the first and second circuitry are formed as separate ASICs.
- 7. An interface circuit for use when coupled between a tester of integrated circuits (ICs) and two or more devices under test (DUTs), comprising:
an input for receiving test data and addresses from a channel of the tester; an output for writing said test data to the DUTs; and comparison circuitry providing error information in response to performing a comparison using data read from each of the DUTs to determine errors, if any, in said DUTs.
- 8. The interface circuit of claim 7 wherein the comparison circuitry provides error information in response to performing the comparison using data read from the DUTs and expected data received over the channel of the tester.
- 9. The interface circuit of claim 7 wherein the comparison circuitry provides compressed error information in response to performing the comparison.
- 10. The interface circuit of claim 9 wherein the compressed error information is provided to the tester over the channel in response to a read request received from the tester over the channel.
- 11a. The interface circuit of claim 10 wherein the compressed information indicates whether an error was determined in any one or more of said DUTs.
- 11b. The interface circuit of claim 11 wherein the compressed information does not indicate an exact bit location of said error.
- 12. An interface circuit for testing a plurality of DUTs, comprising:
means for receiving a data value and an associated address as part of a test sequence; means for delivering a plurality of copies of said data value at a plurality of addresses each corresponding to said associated address; means for receiving a plurality of copies of read data values associated with said plurality of addresses; and means for performing comparisons using said plurality of copies of read data values to generate error values representing differences, if any, between said plurality of copies of read data values and said data value.
- 13. A method for testing a plurality of DUTs, comprising:
receiving a data value and an associated address as part of a test sequence; delivering a plurality of copies of said data value at a plurality of addresses each corresponding to said associated address; receiving a plurality of copies of read data values associated with said plurality of addresses; and performing comparisons using said plurality of copies of read data values to generate error values representing differences, if any, between said plurality of copies of read data values and said data value.
Parent Case Info
[0001] The subject matter in this application is related to material in two other U.S. patent applications of Roy and Miller, entitled PARALLEL TESTING OF INTEGRATED CIRCUIT DEVICES USING CROSS-DUT AND WITHIN-DUT COMPARISONS, having Serial No. ______ (P077), and EFFICIENT PARALLEL TESTING OF INTEGRATED CIRCUIT DEVICES USING A KNOWN GOOD DEVICE TO GENERATE EXPECTED RESPONSES, having Serial No. ______ (P078), filed on the same date as this application and expressly incorporated herein by reference.
Continuations (1)
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Number |
Date |
Country |
Parent |
09260463 |
Mar 1999 |
US |
Child |
10289823 |
Nov 2002 |
US |