Ritu Shrivastava

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory cell with resistance-switching layers and lateral arrangement
- Patent number 8,395,926
- Issue date Mar 12, 2013
- Sandisk 3D LLC
- Franz Kreupl
- G11 - INFORMATION STORAGE
Information Patent Grant
Processing systems and methods for molecular memory
- Patent number 7,799,598
- Issue date Sep 21, 2010
- ZettaCore, Inc.
- Werner G. Kuhr
- G11 - INFORMATION STORAGE
Information Patent Grant
Molecular memory devices including solid-state dielectric layers an...
- Patent number 7,642,546
- Issue date Jan 5, 2010
- ZettaCore, Inc.
- Veena Misra
- G11 - INFORMATION STORAGE
Information Patent Grant
Processing systems and methods for molecular memory
- Patent number 7,358,113
- Issue date Apr 15, 2008
- ZettaCore, Inc.
- Ritu Shrivastava
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of and apparatus for integrating flash EPROM and SRAM cells...
- Patent number 6,921,688
- Issue date Jul 26, 2005
- Alliance Semiconductor
- Ritu Shrivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for integrating flash EPROM and SRAM cells on...
- Patent number 6,903,434
- Issue date Jun 7, 2005
- Alliance Semiconductors
- Ritu Shrivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor chip that isolates DRAM cells from the peripheral cir...
- Patent number 6,589,834
- Issue date Jul 8, 2003
- Alliance Semiconductor Corporation
- Chitranjan N. Reddy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
DRAM cell having storage capacitor contact self-aligned to bit line...
- Patent number 6,472,267
- Issue date Oct 29, 2002
- Alliance Semiconductor Corporation
- Ritu Shrivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flash EPROM memory cell having increased capacitive coupling and me...
- Patent number 6,429,076
- Issue date Aug 6, 2002
- Alliance Semiconductor Corporation
- Perumal Ratnam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flash EPROM array with self-aligned source contacts and programmabl...
- Patent number 6,392,267
- Issue date May 21, 2002
- Alliance Semiconductor Corporation
- Ritu Shrivastava
- G11 - INFORMATION STORAGE
Information Patent Grant
DRAM cell having storage capacitor contact self-aligned to bit line...
- Patent number 6,373,089
- Issue date Apr 16, 2002
- Alliance Semiconductor Corporation
- Ritu Shrivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned contacts for salicided MOS devices
- Patent number 6,258,714
- Issue date Jul 10, 2001
- Alliance Semiconductor Corporation
- Ritu Shrivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flash EPROM memory cell having increased capacitive coupling
- Patent number 6,166,409
- Issue date Dec 26, 2000
- Alliance Semiconductor Corporation
- Perumal Ratnam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of reducing dielectric damage due to charging in the fabrica...
- Patent number 6,133,602
- Issue date Oct 17, 2000
- Alliance Semiconductor Corporation
- Ritu Shrivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of reducing dielectric damage due to charging in the fabrica...
- Patent number 6,020,237
- Issue date Feb 1, 2000
- Alliance Semiconductor Corporation
- Ritu Shrivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
DRAM cell having storage capacitor contact self-aligned to bit line...
- Patent number 5,994,730
- Issue date Nov 30, 1999
- Alliance Semiconductor Corporation
- Ritu Shrivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-converging over-erase repair method for flash EPROM
- Patent number 5,856,944
- Issue date Jan 5, 1999
- Alliance Semiconductor Corporation
- Bruce L. Prickett
- G11 - INFORMATION STORAGE
Information Patent Grant
Reliable edge cell array design
- Patent number 5,731,606
- Issue date Mar 24, 1998
- Ritu Shrivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dynamic random access memory cell having increased capacitance
- Patent number 5,701,264
- Issue date Dec 23, 1997
- Alliance Semiconductor Corporation
- Ritu Shrivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating DRAM cell with self-aligned contact
- Patent number 5,672,535
- Issue date Sep 30, 1997
- Alliance Semiconductor Corporation
- Ritu Shrivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor electrode having improved grain structure and oxide g...
- Patent number 5,557,122
- Issue date Sep 17, 1996
- Alliance Semiconductors Corporation
- Ritu Shrivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making flash EPROM cell having improved erase characteris...
- Patent number 5,518,942
- Issue date May 21, 1996
- Alliance Semiconductor Corporation
- Ritu Shrivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Single transistor flash EPROM cell and method of operation
- Patent number 5,416,738
- Issue date May 16, 1995
- Alliance Semiconductor Corporation
- Ritu Shrivastava
- G11 - INFORMATION STORAGE
Information Patent Grant
Rapid thermal nitridized oxide locos process
- Patent number 4,764,248
- Issue date Aug 16, 1988
- Cypress Semiconductor Corporation
- Arya Bhattacherjee
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Memory Cell With Resistance-Switching Layers And Lateral Arrangement
- Publication number 20110310654
- Publication date Dec 22, 2011
- Franz Kreupl
- G11 - INFORMATION STORAGE
Information Patent Application
Processing Systems and Methods for Molecular Memory
- Publication number 20080219041
- Publication date Sep 11, 2008
- Werner G. Kuhr
- G11 - INFORMATION STORAGE
Information Patent Application
Molecular memory devices including solid-state dielectric layers an...
- Publication number 20070164374
- Publication date Jul 19, 2007
- Veena Misra
- G11 - INFORMATION STORAGE
Information Patent Application
Processing systems and methods for molecular memory
- Publication number 20050270822
- Publication date Dec 8, 2005
- Ritu Shrivastava
- G11 - INFORMATION STORAGE
Information Patent Application
Method of and apparatus for integrating flash EPROM and SRAM cells...
- Publication number 20030151111
- Publication date Aug 14, 2003
- RITU SHRIVASTAVA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR INTEGRATING FLASH EPROM AND SRAM CELLS ON...
- Publication number 20020089029
- Publication date Jul 11, 2002
- RITU SHRIVASTAVA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Interconnect to plate contact/via arrangement for random access memory
- Publication number 20020081802
- Publication date Jun 27, 2002
- Ritu Shrivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DRAM cell having storage capacitor contact self-aligned to bit line...
- Publication number 20020053692
- Publication date May 9, 2002
- Alliance Semiconductor Corporation
- Ritu Shrivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Flash eprom memory cell having increased capacitive coupling and me...
- Publication number 20010015920
- Publication date Aug 23, 2001
- Alliance Semiconductor Corporation
- Perumal Ratnam
- H01 - BASIC ELECTRIC ELEMENTS

Ritu Shrivastava

Person

Patents Grantslast 30 patents

Memory cell with resistance-switching layers and lateral arrangement

Processing systems and methods for molecular memory

Molecular memory devices including solid-state dielectric layers an...

Processing systems and methods for molecular memory

Method of and apparatus for integrating flash EPROM and SRAM cells...

Method and apparatus for integrating flash EPROM and SRAM cells on...

Semiconductor chip that isolates DRAM cells from the peripheral cir...

DRAM cell having storage capacitor contact self-aligned to bit line...

Flash EPROM memory cell having increased capacitive coupling and me...

Flash EPROM array with self-aligned source contacts and programmabl...

DRAM cell having storage capacitor contact self-aligned to bit line...

Self-aligned contacts for salicided MOS devices

Flash EPROM memory cell having increased capacitive coupling

Method of reducing dielectric damage due to charging in the fabrica...

Method of reducing dielectric damage due to charging in the fabrica...

DRAM cell having storage capacitor contact self-aligned to bit line...

Self-converging over-erase repair method for flash EPROM

Reliable edge cell array design

Dynamic random access memory cell having increased capacitance

Method of fabricating DRAM cell with self-aligned contact

Semiconductor electrode having improved grain structure and oxide g...

Method of making flash EPROM cell having improved erase characteris...

Single transistor flash EPROM cell and method of operation

Rapid thermal nitridized oxide locos process

Patents Applicationslast 30 patents

Memory Cell With Resistance-Switching Layers And Lateral Arrangement

Processing Systems and Methods for Molecular Memory

Molecular memory devices including solid-state dielectric layers an...

Processing systems and methods for molecular memory

Method of and apparatus for integrating flash EPROM and SRAM cells...

METHOD AND APPARATUS FOR INTEGRATING FLASH EPROM AND SRAM CELLS ON...

Interconnect to plate contact/via arrangement for random access memory

DRAM cell having storage capacitor contact self-aligned to bit line...

Flash eprom memory cell having increased capacitive coupling and me...