Ruiqi Tian

Person

Pflugerville, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated assist features for epitaxial growth
- Patent number 8,741,743
- Issue date Jun 3, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Omar Zia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated assist features for epitaxial growth
- Patent number 8,722,519
- Issue date May 13, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Omar Zia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for reducing plasma discharge damage during processing
- Patent number 8,343,842
- Issue date Jan 1, 2013
- FREESCALE SEMICONDUCTOR, INC.
- David M. Schraub
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated assist features for epitaxial growth
- Patent number 8,003,539
- Issue date Aug 23, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Omar Zia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for reducing plasma discharge damage during processing
- Patent number 7,951,695
- Issue date May 31, 2011
- FREESCALE SEMICONDUCTOR, INC.
- David M. Schraub
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having tiles for dual-trench integration and m...
- Patent number 7,785,983
- Issue date Aug 31, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Omar Zia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a semiconductor device having dummy features
- Patent number 7,741,221
- Issue date Jun 22, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Ruiqi Tian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated assist features for epitaxial growth bulk tiles with com...
- Patent number 7,565,639
- Issue date Jul 21, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Omar Zia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated assist features for epitaxial growth bulk/SOI hybrid til...
- Patent number 7,470,624
- Issue date Dec 30, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Omar Zia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of implementing polishing uniformity and modifying layout data
- Patent number 7,322,014
- Issue date Jan 22, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Edward O. Travis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Die level metal density gradient for improved flip chip package rel...
- Patent number 7,276,435
- Issue date Oct 2, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Scott K. Pozder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of implementing polishing uniformity and modifying layout data
- Patent number 7,146,593
- Issue date Dec 5, 2006
- FREESCALE SEMICONDUCTOR, INC.
- Edward O. Travis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for improving planarity of shallow trench isolation using mu...
- Patent number 6,905,967
- Issue date Jun 14, 2005
- AMD, Inc.
- Ruiqi Tian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming an integrated circuit device using dummy features...
- Patent number 6,611,045
- Issue date Aug 26, 2003
- Motorola, Inc.
- Edward O. Travis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for adding features to a design layout and process for desig...
- Patent number 6,593,226
- Issue date Jul 15, 2003
- Motorola, Inc.
- Edward O. Travis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective sizing of features to compensate for resist thickness var...
- Patent number 6,489,083
- Issue date Dec 3, 2002
- Motorola, Inc.
- Bradley P. Smith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device, a process for a semiconductor device, and a p...
- Patent number 6,459,156
- Issue date Oct 1, 2002
- Motorola, Inc.
- Edward O. Travis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and a process for designing a mask
- Patent number 6,396,158
- Issue date May 28, 2002
- Motorola Inc.
- Edward O. Travis
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Integrated Assist Features for Epitaxial Growth
- Publication number 20110269300
- Publication date Nov 3, 2011
- Freescale Semiconductor Inc.
- Omar Zia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Reducing Plasma Discharge Damage During Processing
- Publication number 20110179394
- Publication date Jul 21, 2011
- David M. Schraub
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Reducing Plasma Discharge Damage During Processing
- Publication number 20090291547
- Publication date Nov 26, 2009
- David M. Schraub
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE HAVING TILES FOR DUAL-TRENCH INTEGRATION AND M...
- Publication number 20080217714
- Publication date Sep 11, 2008
- Omar Zia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated assist features for epitaxial growth
- Publication number 20080166859
- Publication date Jul 10, 2008
- Freescale Semiconductor, Inc.
- Omar Zia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated assist features for epitaxial growth bulk/SOI hybrid til...
- Publication number 20080168418
- Publication date Jul 10, 2008
- Freescale Semiconductor, Inc.
- Omar Zia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated assist features for epitaxial growth
- Publication number 20080164559
- Publication date Jul 10, 2008
- Freescale Semiconductor, Inc.
- Omar Zia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated assist features for epitaxial growth bulk tiles with com...
- Publication number 20080168417
- Publication date Jul 10, 2008
- Freescale Semiconductor, Inc.
- Omar Zia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of forming a semiconductor device having dummy features
- Publication number 20070134921
- Publication date Jun 14, 2007
- Ruiqi Tian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF IMPLEMENTING POLISHING UNIFORMITY AND MODIFYING LAYOUT DATA
- Publication number 20070061768
- Publication date Mar 15, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Edward O. Travis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of implementing polishing uniformity and modifying layout data
- Publication number 20050097490
- Publication date May 5, 2005
- Edward O. Travis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of forming an integrated circuit device using dummy features...
- Publication number 20020179902
- Publication date Dec 5, 2002
- Edward O. Travis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for adding features to a design layout and process for desig...
- Publication number 20020050655
- Publication date May 2, 2002
- Edward O. Travis
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Integrated assist features for epitaxial growth

Integrated assist features for epitaxial growth

Method for reducing plasma discharge damage during processing

Integrated assist features for epitaxial growth

Method for reducing plasma discharge damage during processing

Semiconductor device having tiles for dual-trench integration and m...

Method of forming a semiconductor device having dummy features

Integrated assist features for epitaxial growth bulk tiles with com...

Integrated assist features for epitaxial growth bulk/SOI hybrid til...

Method of implementing polishing uniformity and modifying layout data

Die level metal density gradient for improved flip chip package rel...

Method of implementing polishing uniformity and modifying layout data

Method for improving planarity of shallow trench isolation using mu...

Method of forming an integrated circuit device using dummy features...

Method for adding features to a design layout and process for desig...

Selective sizing of features to compensate for resist thickness var...

Semiconductor device, a process for a semiconductor device, and a p...

Semiconductor device and a process for designing a mask

Patents Applicationslast 30 patents

Integrated Assist Features for Epitaxial Growth

Method for Reducing Plasma Discharge Damage During Processing

Method for Reducing Plasma Discharge Damage During Processing

SEMICONDUCTOR DEVICE HAVING TILES FOR DUAL-TRENCH INTEGRATION AND M...

Integrated assist features for epitaxial growth

Integrated assist features for epitaxial growth bulk/SOI hybrid til...

Integrated assist features for epitaxial growth

Integrated assist features for epitaxial growth bulk tiles with com...

Method of forming a semiconductor device having dummy features

METHOD OF IMPLEMENTING POLISHING UNIFORMITY AND MODIFYING LAYOUT DATA

Method of implementing polishing uniformity and modifying layout data

Method of forming an integrated circuit device using dummy features...

Method for adding features to a design layout and process for desig...