Sebastian Ehrenreich

Person

Schoenau, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Signal repowering chip for 3-dimensional integrated circuit
- Patent number 8,513,663
- Issue date Aug 20, 2013
- International Business Machines Corporation
- Markus Buehler
- G01 - MEASURING TESTING
Information Patent Grant
On-die voltage regulation using p-FET header devices with a feedbac...
- Patent number 8,476,966
- Issue date Jul 2, 2013
- International Business Machines Corporation
- Thomas Buechner
- G05 - CONTROLLING REGULATING
Information Patent Grant
Method, system, computer program product, and data processing devic...
- Patent number 8,363,487
- Issue date Jan 29, 2013
- International Business Machines Corporation
- Sebastian Ehrenreich
- G11 - INFORMATION STORAGE
Information Patent Grant
Wordline booster design structure and method of operating a wordine...
- Patent number 7,921,388
- Issue date Apr 5, 2011
- International Business Machines Corporation
- Sebastian Ehrenreich
- G11 - INFORMATION STORAGE
Information Patent Grant
Single-ended read and differential write scheme
- Patent number 7,813,163
- Issue date Oct 12, 2010
- International Business Machines Corporation
- Juergen Pille
- G11 - INFORMATION STORAGE
Information Patent Grant
Method to reduce leakage of a SRAM-array
- Patent number 7,808,856
- Issue date Oct 5, 2010
- International Business Machines Corporation
- Sebastian Ehrenreich
- G11 - INFORMATION STORAGE
Information Patent Grant
Redundancy in signal distribution trees
- Patent number 7,755,408
- Issue date Jul 13, 2010
- International Business Machines Corporation
- Sebastian Ehrenreich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Design structure for improving performance of SRAM cells, SRAM cell...
- Patent number 7,675,794
- Issue date Mar 9, 2010
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Wordline booster circuit and method of operating a wordline booster...
- Patent number 7,636,254
- Issue date Dec 22, 2009
- International Business Machines Corporation
- Sebastian Ehrenreich
- G11 - INFORMATION STORAGE
Information Patent Grant
Method to improve performance of SRAM cells, SRAM cell, SRAM array,...
- Patent number 7,626,851
- Issue date Dec 1, 2009
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Storage cell design evaluation circuit including a wordline timing...
- Patent number 7,564,739
- Issue date Jul 21, 2009
- International Business Machines Corporation
- Sebastian Ehrenreich
- G11 - INFORMATION STORAGE
Information Patent Grant
Bypass circuit for memory arrays
- Patent number 7,558,138
- Issue date Jul 7, 2009
- International Business Machines Corporation
- Sebastian Ehrenreich
- G11 - INFORMATION STORAGE
Information Patent Grant
Asymmetrical random access memory cell, and a memory comprising asy...
- Patent number 7,535,750
- Issue date May 19, 2009
- International Business Machines Corporation
- Otto Wagner
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for evaluating storage cell design using a wordline timing a...
- Patent number 7,414,904
- Issue date Aug 19, 2008
- International Business Machines Corporation
- Sebastian Ehrenreich
- G11 - INFORMATION STORAGE
Information Patent Grant
Redundancy in signal distribution trees
- Patent number 7,336,115
- Issue date Feb 26, 2008
- International Business Machines Corporation
- Sebastian Ehrenreich
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
On-Die Voltage Regulation Using p-FET Header Devices with a Feedbac...
- Publication number 20120081176
- Publication date Apr 5, 2012
- International Business Machines Corporation
- Thomas Buechner
- G05 - CONTROLLING REGULATING
Information Patent Application
METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND DATA PROCESSING DEVIC...
- Publication number 20100309734
- Publication date Dec 9, 2010
- IBM Corporation
- Sebastian Ehrenreich
- G11 - INFORMATION STORAGE
Information Patent Application
Signal Repowering Chip For 3-Dimensional Integrated Circuit
- Publication number 20100237700
- Publication date Sep 23, 2010
- International Business Machines Corporation
- Markus Buehler
- G01 - MEASURING TESTING
Information Patent Application
METHOD TO REDUCE LEAKAGE OF A SRAM-ARRAY
- Publication number 20090285046
- Publication date Nov 19, 2009
- Sebastian Ehrenreich
- G11 - INFORMATION STORAGE
Information Patent Application
DESIGN STRUCTURE FOR IMPROVING PERFORMANCE OF SRAM CELLS, SRAM CELL...
- Publication number 20090154263
- Publication date Jun 18, 2009
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
Single-ended read and differential write scheme
- Publication number 20090059688
- Publication date Mar 5, 2009
- International Business Machines Corporation
- Juergen Pille
- G11 - INFORMATION STORAGE
Information Patent Application
STORAGE CELL DESIGN EVALUATION CIRCUIT INCLUDING A WORDLINE TIMING...
- Publication number 20080273403
- Publication date Nov 6, 2008
- International Business Machines Corporation
- Sebastian Ehrenreich
- G11 - INFORMATION STORAGE
Information Patent Application
Redundancy in Signal Distribution Trees
- Publication number 20080256413
- Publication date Oct 16, 2008
- International Business Machines Corporation
- Sebastian Ehrenreich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Comparator Circuit and Method for Operating a Comparator Circuit
- Publication number 20080178129
- Publication date Jul 24, 2008
- International Business Machines Corporation
- Sebastian Ehrenreich
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD TO IMPROVE PERFORMANCE OF SRAM CELLS, SRAM CELL, SRAM ARRAY,...
- Publication number 20080123442
- Publication date May 29, 2008
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
Wordline Booster Design Structure and Method of Operating a Wordlin...
- Publication number 20080068902
- Publication date Mar 20, 2008
- Sebastian Ehrenreich
- G11 - INFORMATION STORAGE
Information Patent Application
Wordline Booster Circuit and Method of Operating a Wordline Booster...
- Publication number 20080068901
- Publication date Mar 20, 2008
- Sebastian Ehrenreich
- G11 - INFORMATION STORAGE
Information Patent Application
Comparator Circuit and Method for Operating a Comparator Circuit
- Publication number 20080048729
- Publication date Feb 28, 2008
- International Business Machines Corporation
- Sebastian Ehrenreich
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Circuit Arrangement and Method to Reduce Leakage Power and to Incre...
- Publication number 20070165343
- Publication date Jul 19, 2007
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Asymmetrical Random Access Memory Cell, A Memory Comprising Asymmet...
- Publication number 20070165447
- Publication date Jul 19, 2007
- Otto Wagner
- G11 - INFORMATION STORAGE
Information Patent Application
Redundancy in signal distribution trees
- Publication number 20060179396
- Publication date Aug 10, 2006
- International Business Machines Corporation
- Sebastian Ehrenreich
- G06 - COMPUTING CALCULATING COUNTING

Sebastian Ehrenreich

Person

Patents Grantslast 30 patents

Signal repowering chip for 3-dimensional integrated circuit

On-die voltage regulation using p-FET header devices with a feedbac...

Method, system, computer program product, and data processing devic...

Wordline booster design structure and method of operating a wordine...

Single-ended read and differential write scheme

Method to reduce leakage of a SRAM-array

Redundancy in signal distribution trees

Design structure for improving performance of SRAM cells, SRAM cell...

Wordline booster circuit and method of operating a wordline booster...

Method to improve performance of SRAM cells, SRAM cell, SRAM array,...

Storage cell design evaluation circuit including a wordline timing...

Bypass circuit for memory arrays

Asymmetrical random access memory cell, and a memory comprising asy...

Method for evaluating storage cell design using a wordline timing a...

Redundancy in signal distribution trees

Patents Applicationslast 30 patents

On-Die Voltage Regulation Using p-FET Header Devices with a Feedbac...

METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND DATA PROCESSING DEVIC...

Signal Repowering Chip For 3-Dimensional Integrated Circuit

METHOD TO REDUCE LEAKAGE OF A SRAM-ARRAY

DESIGN STRUCTURE FOR IMPROVING PERFORMANCE OF SRAM CELLS, SRAM CELL...

Single-ended read and differential write scheme

STORAGE CELL DESIGN EVALUATION CIRCUIT INCLUDING A WORDLINE TIMING...

Redundancy in Signal Distribution Trees

Comparator Circuit and Method for Operating a Comparator Circuit

METHOD TO IMPROVE PERFORMANCE OF SRAM CELLS, SRAM CELL, SRAM ARRAY,...

Wordline Booster Design Structure and Method of Operating a Wordlin...

Wordline Booster Circuit and Method of Operating a Wordline Booster...

Comparator Circuit and Method for Operating a Comparator Circuit

Circuit Arrangement and Method to Reduce Leakage Power and to Incre...

Asymmetrical Random Access Memory Cell, A Memory Comprising Asymmet...

Redundancy in signal distribution trees