Shiann-Ming Liou

Person

Campbell, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Removable non-volatile storage card
- Patent number 11,308,380
- Issue date Apr 19, 2022
- INNOGRIT TECHNOLOGIES CO., LTD.
- Abhilash Mathew
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ground reference shape for high speed interconnect
- Patent number 11,276,655
- Issue date Mar 15, 2022
- InnogritTechnologies Co., Ltd.
- Shiann-Ming Liou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor die with hybrid wire bond pads
- Patent number 11,043,435
- Issue date Jun 22, 2021
- INNOGRIT TECHNOLOGIES CO., LTD.
- Lin Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Leadframe with improved half-etch layout to reduce defects caused d...
- Patent number 10,128,171
- Issue date Nov 13, 2018
- Marvell International Ltd.
- Huahung Kao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package assembly including a semiconductor substrate in which a fir...
- Patent number 9,768,144
- Issue date Sep 19, 2017
- Marvell World Trade Ltd.
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package-on-package structures
- Patent number 9,666,571
- Issue date May 30, 2017
- Marvell World Trade Ltd.
- Huahung Kao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual row quad flat no-lead semiconductor package
- Patent number 9,666,510
- Issue date May 30, 2017
- Marvell World Trade Ltd.
- Chenglin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pad configurations for an electronic package assembly
- Patent number 9,543,236
- Issue date Jan 10, 2017
- Marvell World Trade Ltd.
- Sehat Sutardja
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual row quad flat no-lead semiconductor package
- Patent number 9,425,139
- Issue date Aug 23, 2016
- Marvell World Trade Ltd.
- Chenglin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Recessed semiconductor substrates and associated techniques
- Patent number 9,391,045
- Issue date Jul 12, 2016
- Marvell World Trade Ltd.
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect layouts for electronic assemblies
- Patent number 9,355,951
- Issue date May 31, 2016
- Marvell World Trade Ltd.
- Huahung Kao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pad configurations for an electronic package assembly
- Patent number 9,331,052
- Issue date May 3, 2016
- Marvell World Trade Ltd.
- Sehat Sutardja
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ball grid array package substrate with through holes and method of...
- Patent number 9,288,909
- Issue date Mar 15, 2016
- Marvell World Trade Ltd.
- Shiann-Ming Liou
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Package assembly having a semiconductor substrate
- Patent number 9,275,929
- Issue date Mar 1, 2016
- Marvell World Trade Ltd.
- Shiann-Ming Liou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package assembly including a semiconductor substrate in which a fir...
- Patent number 9,257,410
- Issue date Feb 9, 2016
- Marvell World Trade Ltd.
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming semiconductor layout
- Patent number 9,252,115
- Issue date Feb 2, 2016
- Marvell International Ltd.
- Thomas Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor die having lead wires formed over a circuit in a shie...
- Patent number 9,240,372
- Issue date Jan 19, 2016
- Marvell International Ltd.
- Shiann-Ming Liou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package
- Patent number 9,224,677
- Issue date Dec 29, 2015
- Marvell International Ltd.
- Shiann-Ming Liou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package-on-package structures
- Patent number 9,209,163
- Issue date Dec 8, 2015
- Marvell World Trade Ltd.
- Huahung Kao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Attaching passive components to a semiconductor package
- Patent number 9,171,744
- Issue date Oct 27, 2015
- Marvell World Trade Ltd.
- Shiann-Ming Liou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of package pins in semiconductor packaging
- Patent number 9,123,699
- Issue date Sep 1, 2015
- Marvell International Ltd.
- Chenglin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with a semiconductor die embedded within subs...
- Patent number 9,070,679
- Issue date Jun 30, 2015
- Marvell World Trade Ltd.
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming one or more vias through a semiconductor substra...
- Patent number 9,064,860
- Issue date Jun 23, 2015
- Marvell International Ltd.
- Shiann-Ming Liou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Recessed semiconductor substrates and associated techniques
- Patent number 9,034,730
- Issue date May 19, 2015
- Marvell World Trade Ltd.
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Etched hybrid die package
- Patent number 8,999,755
- Issue date Apr 7, 2015
- Marvell International Ltd.
- Chenglin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Attaching passive components to a semiconductor package
- Patent number 8,987,830
- Issue date Mar 24, 2015
- Marvell World Trade Ltd.
- Shiann-Ming Liou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Single layer BGA substrate process
- Patent number 8,940,585
- Issue date Jan 27, 2015
- Marvell World Trade Ltd.
- Shiann-Ming Liou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Leadless multi-chip module structure
- Patent number 8,912,664
- Issue date Dec 16, 2014
- Marvell International Ltd.
- Shiann-Ming Liou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thermal enhanced package
- Patent number 8,900,932
- Issue date Dec 2, 2014
- Marvell World Trade Ltd.
- Chenglin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging configurations
- Patent number 8,884,419
- Issue date Nov 11, 2014
- Marvell International Ltd.
- Shiann-Ming Liou
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
CIRCUIT ASSEMBLY WITH THERMAL COATING IN CONTACT WITH EXPOSED METAL...
- Publication number 20220068749
- Publication date Mar 3, 2022
- INNOGRIT TECHNOLOGIES CO., LTD
- Yanwen BAI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EMBEDDED MICROSTRIP WITH OPEN SLOT FOR HIGH SPEED SIGNAL TRACES
- Publication number 20210392742
- Publication date Dec 16, 2021
- INNOGRIT TECHNOLOGIES CO., LTD
- Shiann-Ming LIOU
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
GROUND REFERENCE SHAPE FOR HIGH SPEED INTERCONNECT
- Publication number 20210366848
- Publication date Nov 25, 2021
- INNOGRIT TECHNOLOGIES CO., LTD
- Shiann-Ming LIOU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGING ARRANGEMENTS INCLUDING A SERIALIZING DRAM INTERFACE DIE
- Publication number 20170047305
- Publication date Feb 16, 2017
- Marvell World Trade Ltd.
- Chenglin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL ROW QUAD FLAT NO-LEAD SEMICONDUCTOR PACKAGE
- Publication number 20160358845
- Publication date Dec 8, 2016
- Marvell World Trade Ltd.
- Chenglin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING A VIA STRUCTURE USING A DOUBLE-SIDE LASER PROCESS
- Publication number 20160353585
- Publication date Dec 1, 2016
- Marvell World Trade Ltd.
- Huahung Kao
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
PAD CONFIGURATIONS FOR AN ELECTRONIC PACKAGE ASSEMBLY
- Publication number 20160240459
- Publication date Aug 18, 2016
- Marvell World Trade Ltd.
- Sehat Sutardja
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BALL GRID ARRAY PACKAGE SUBSTRATE WITH THROUGH HOLES AND METHOD OF...
- Publication number 20160196986
- Publication date Jul 7, 2016
- Marvell World Trade Ltd.
- Shiann-Ming Liou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ASSEMBLY INCLUDING A SEMICONDUCTOR SUBSTRATE IN WHICH A FIR...
- Publication number 20160155732
- Publication date Jun 2, 2016
- Marvell World Trade Ltd.
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE-ON-PACKAGE STRUCTURES
- Publication number 20160093602
- Publication date Mar 31, 2016
- Marvell World Trade Ltd.
- Huahung Kao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE WITH A SEMICONDUCTOR DIE EMBEDDED WITHIN SUBS...
- Publication number 20150311147
- Publication date Oct 29, 2015
- Marvell World Trade Ltd.
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RECESSED SEMICONDUCTOR SUBSTRATES AND ASSOCIATED TECHNIQUES
- Publication number 20150279806
- Publication date Oct 1, 2015
- Marvell World Trade Ltd.
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING A VIA STRUCTURE USING A DOUBLE-SIDE LASER PROCESS
- Publication number 20150257281
- Publication date Sep 10, 2015
- Marvell World Trade Ltd.
- Huahung Kao
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
PACKAGE ASSEMBLY HAVING A SEMICONDUCTOR SUBSTRATE
- Publication number 20150221577
- Publication date Aug 6, 2015
- Marvell World Trade Ltd.
- Shiann-Ming Liou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ATTACHING PASSIVE COMPONENTS TO A SEMICONDUCTOR PACKAGE
- Publication number 20150200114
- Publication date Jul 16, 2015
- Marvell World Trade Ltd.
- Shiann-Ming Liou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PAD CONFIGURATIONS FOR AN ELECTRONIC PACKAGE ASSEMBLY
- Publication number 20150035160
- Publication date Feb 5, 2015
- Marvell World Trade Ltd.
- Sehat Sutardja
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SINGLE LAYER BGA SUBSTRATE PROCESS
- Publication number 20140206152
- Publication date Jul 24, 2014
- Marvell World Trade Ltd.
- Shiann-Ming Liou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE-ON-PACKAGE STRUCTURES
- Publication number 20140151880
- Publication date Jun 5, 2014
- Marvell World Trade Ltd.
- Huahung Kao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES AND CONFIGURATIONS FOR RECESSED SEMICONDUCTOR SUBSTRATES
- Publication number 20140124961
- Publication date May 8, 2014
- Marvell World Trade Ltd.
- Albert WU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL ROW QUAD FLAT NO-LEAD SEMICONDUCTOR PACKAGE
- Publication number 20140069703
- Publication date Mar 13, 2014
- Marvell World Trade Ltd.
- Chenglin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BALL GRID ARRAY PACKAGE SUBSTRATE WITH THROUGH HOLES AND METHOD OF...
- Publication number 20130193572
- Publication date Aug 1, 2013
- Marvell World Trade Ltd.
- Shiann-Ming Liou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF STACKING FLIP-CHIP ON WIRE-BONDED CHIP
- Publication number 20130147025
- Publication date Jun 13, 2013
- Marvell World Trade Ltd.
- Shiann-Ming Liou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP ON LEADS
- Publication number 20130045573
- Publication date Feb 21, 2013
- Marvell World Trade Ltd.
- Chenglin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE-ON-PACKAGE STRUCTURES
- Publication number 20130043587
- Publication date Feb 21, 2013
- Huahung Kao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THERMAL ENHANCED PACKAGE
- Publication number 20130011964
- Publication date Jan 10, 2013
- MARVEL WORLD TRADE LTD.
- Chenglin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SINGLE LAYER BGA SUBSTRATE PROCESS
- Publication number 20120196407
- Publication date Aug 2, 2012
- Shiann-Ming Liou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PAD CONFIGURATIONS FOR AN ELECTRONIC PACKAGE ASSEMBLY
- Publication number 20110298117
- Publication date Dec 8, 2011
- Sehat Sutardja
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES AND CONFIGURATIONS FOR RECESSED SEMICONDUCTOR SUBSTRATES
- Publication number 20110186960
- Publication date Aug 4, 2011
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RECESSED SEMICONDUCTOR SUBSTRATES AND ASSOCIATED TECHNIQUES
- Publication number 20110186992
- Publication date Aug 4, 2011
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RECESSED SEMICONDUCTOR SUBSTRATES
- Publication number 20110186998
- Publication date Aug 4, 2011
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS

Shiann-Ming Liou

Person

Patents Grantslast 30 patents

Removable non-volatile storage card

Ground reference shape for high speed interconnect

Semiconductor die with hybrid wire bond pads

Leadframe with improved half-etch layout to reduce defects caused d...

Package assembly including a semiconductor substrate in which a fir...

Package-on-package structures

Dual row quad flat no-lead semiconductor package

Pad configurations for an electronic package assembly

Dual row quad flat no-lead semiconductor package

Recessed semiconductor substrates and associated techniques

Interconnect layouts for electronic assemblies

Pad configurations for an electronic package assembly

Ball grid array package substrate with through holes and method of...

Package assembly having a semiconductor substrate

Package assembly including a semiconductor substrate in which a fir...

Method for forming semiconductor layout

Semiconductor die having lead wires formed over a circuit in a shie...

Semiconductor package

Package-on-package structures

Attaching passive components to a semiconductor package

Formation of package pins in semiconductor packaging

Semiconductor package with a semiconductor die embedded within subs...

Method for forming one or more vias through a semiconductor substra...

Recessed semiconductor substrates and associated techniques

Etched hybrid die package

Attaching passive components to a semiconductor package

Single layer BGA substrate process

Leadless multi-chip module structure

Thermal enhanced package

Integrated circuit packaging configurations

Patents Applicationslast 30 patents

CIRCUIT ASSEMBLY WITH THERMAL COATING IN CONTACT WITH EXPOSED METAL...

EMBEDDED MICROSTRIP WITH OPEN SLOT FOR HIGH SPEED SIGNAL TRACES

GROUND REFERENCE SHAPE FOR HIGH SPEED INTERCONNECT

PACKAGING ARRANGEMENTS INCLUDING A SERIALIZING DRAM INTERFACE DIE

DUAL ROW QUAD FLAT NO-LEAD SEMICONDUCTOR PACKAGE

METHOD FOR FORMING A VIA STRUCTURE USING A DOUBLE-SIDE LASER PROCESS

PAD CONFIGURATIONS FOR AN ELECTRONIC PACKAGE ASSEMBLY

BALL GRID ARRAY PACKAGE SUBSTRATE WITH THROUGH HOLES AND METHOD OF...

PACKAGE ASSEMBLY INCLUDING A SEMICONDUCTOR SUBSTRATE IN WHICH A FIR...

PACKAGE-ON-PACKAGE STRUCTURES

SEMICONDUCTOR PACKAGE WITH A SEMICONDUCTOR DIE EMBEDDED WITHIN SUBS...

RECESSED SEMICONDUCTOR SUBSTRATES AND ASSOCIATED TECHNIQUES

METHOD FOR FORMING A VIA STRUCTURE USING A DOUBLE-SIDE LASER PROCESS

PACKAGE ASSEMBLY HAVING A SEMICONDUCTOR SUBSTRATE

ATTACHING PASSIVE COMPONENTS TO A SEMICONDUCTOR PACKAGE

PAD CONFIGURATIONS FOR AN ELECTRONIC PACKAGE ASSEMBLY

SINGLE LAYER BGA SUBSTRATE PROCESS

PACKAGE-ON-PACKAGE STRUCTURES

TECHNIQUES AND CONFIGURATIONS FOR RECESSED SEMICONDUCTOR SUBSTRATES

DUAL ROW QUAD FLAT NO-LEAD SEMICONDUCTOR PACKAGE

BALL GRID ARRAY PACKAGE SUBSTRATE WITH THROUGH HOLES AND METHOD OF...

METHOD OF STACKING FLIP-CHIP ON WIRE-BONDED CHIP

CHIP ON LEADS

PACKAGE-ON-PACKAGE STRUCTURES

THERMAL ENHANCED PACKAGE

SINGLE LAYER BGA SUBSTRATE PROCESS

PAD CONFIGURATIONS FOR AN ELECTRONIC PACKAGE ASSEMBLY

TECHNIQUES AND CONFIGURATIONS FOR RECESSED SEMICONDUCTOR SUBSTRATES

RECESSED SEMICONDUCTOR SUBSTRATES AND ASSOCIATED TECHNIQUES

RECESSED SEMICONDUCTOR SUBSTRATES