Steve K. Hsia

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory element with a reactive metal layer
- Patent number 11,502,249
- Issue date Nov 15, 2022
- Hefei Reliance Memory Limited
- Christophe J. Chevallier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory element with a reactive metal layer
- Patent number 10,833,125
- Issue date Nov 10, 2020
- Hefei Reliance Memory Limited
- Christophe J. Chevallier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory element with a reactive metal layer
- Patent number 10,797,106
- Issue date Oct 6, 2020
- Hefei Reliance Memory Limited
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory element with a reactive metal layer
- Patent number 10,340,312
- Issue date Jul 2, 2019
- Hefei Reliance Memory Limited
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory element with a reactive metal layer
- Patent number 9,806,130
- Issue date Oct 31, 2017
- Unity Semiconductor Corporation
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory element with a reactive metal layer
- Patent number 9,570,515
- Issue date Feb 14, 2017
- Unity Semiconductor Corporation
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory element with a reactive metal layer
- Patent number 9,159,408
- Issue date Oct 13, 2015
- Unity Semiconductor Corporation
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory element with a reactive metal layer
- Patent number 8,675,389
- Issue date Mar 18, 2014
- Unity Semiconductor Corporation
- Christophe Chevallier
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for fabricating multi-resistive state memory devices
- Patent number 8,611,130
- Issue date Dec 17, 2013
- Unity Semiconductor Corporation
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Grant
Low temperature deposition of complex metal oxides (CMO) memory mat...
- Patent number 7,063,984
- Issue date Jun 20, 2006
- Unity Semiconductor Corporation
- Makoto Nagashima
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Virtual ground single transistor memory cell, memory array incorpor...
- Patent number 6,873,004
- Issue date Mar 29, 2005
- NexFlash Technologies, Inc.
- Kyung Joon Han
- G11 - INFORMATION STORAGE
Information Patent Grant
Cross point memory array using multiple modes of operation
- Patent number 6,834,008
- Issue date Dec 21, 2004
- Unity Semiconductor Corporation
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Grant
Cross point memory array using distinct voltages
- Patent number 6,831,854
- Issue date Dec 14, 2004
- Unity Semiconductor Corporation
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-output multiplexor
- Patent number 6,798,685
- Issue date Sep 28, 2004
- Unity Semiconductor Corporation
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Grant
Cross point memory array using multiple thin films
- Patent number 6,753,561
- Issue date Jun 22, 2004
- Unity Semiconductor Corporation
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for multiple byte or page mode programming of...
- Patent number 6,747,899
- Issue date Jun 8, 2004
- NexFlash Technologies, Inc.
- Steve K. Hsia
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for multiple byte or page mode programming of...
- Patent number 6,731,544
- Issue date May 4, 2004
- NexFlash Technologies, Inc.
- Kyung Joon Han
- G11 - INFORMATION STORAGE
Information Patent Grant
Threshold voltage convergence
- Patent number 6,728,140
- Issue date Apr 27, 2004
- NexFlash Technologies, Inc.
- Kyung Joon Han
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-aligned stack formation
- Patent number 6,562,724
- Issue date May 13, 2003
- Texas Instruments Incorporated
- Steve Hsia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low defect density composite dielectric
- Patent number 5,969,397
- Issue date Oct 19, 1999
- Texas Instruments Incorporated
- Douglas Ticknor Grider
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory circuit with pumped voltage for erase and program operations
- Patent number 5,313,429
- Issue date May 17, 1994
- Catalyst Semiconductor, Inc.
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array architecture for flash memory
- Patent number 5,185,718
- Issue date Feb 9, 1993
- Catalyst Semiconductor Corporation
- Darrell D. Rinerson
- G11 - INFORMATION STORAGE
Information Patent Grant
High density EEPROM cell and process for making the cell
- Patent number 5,033,023
- Issue date Jul 16, 1991
- Catalyst Semiconductor, Inc.
- Steve K. Hsia
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile memory cell for eeprom including a floating gate to dra...
- Patent number 4,894,802
- Issue date Jan 16, 1990
- Catalyst Semiconductor, Inc.
- Steve K. Hsia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for making a high density split gate nonvolatile memory cell
- Patent number 4,861,730
- Issue date Aug 29, 1989
- Catalyst Semiconductor, Inc.
- Steve K. Hsia
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY ELEMENT WITH A REACTIVE METAL LAYER
- Publication number 20210013262
- Publication date Jan 14, 2021
- Hefei Reliance Memory Limited
- Christophe J. CHEVALLIER
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ELEMENT WITH A REACTIVE METAL LAYER
- Publication number 20190305047
- Publication date Oct 3, 2019
- Hefei Reliance Memory Limited
- Christophe J. CHEVALLIER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY ELEMENT WITH A REACTIVE METAL LAYER
- Publication number 20180122857
- Publication date May 3, 2018
- UNITY SEMICONDUCTOR CORPORATION
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ELEMENT WITH A REACTIVE METAL LAYER
- Publication number 20170179197
- Publication date Jun 22, 2017
- UNITY SEMICONDUCTOR CORPORATION
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ELEMENT WITH A REACTIVE METAL LAYER
- Publication number 20160005793
- Publication date Jan 7, 2016
- UNITY SEMICONDUCTOR CORPORATION
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Element With a Reactive Metal Layer
- Publication number 20140211542
- Publication date Jul 31, 2014
- UNITY SEMICONDUCTOR CORPORATION
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Application
Conductive memory stack with sidewall
- Publication number 20070158716
- Publication date Jul 12, 2007
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Application
Multi-resistive state element with reactive metal
- Publication number 20060245243
- Publication date Nov 2, 2006
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ELEMENT HAVING ISLANDS
- Publication number 20050243595
- Publication date Nov 3, 2005
- UNITY SEMICONDUCTOR CORPORATION
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Application
Multi-resistive state element with reactive metal
- Publication number 20050174835
- Publication date Aug 11, 2005
- UNITY SEMICONDUCTOR CORPORATION
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Application
CONDUCTIVE MEMORY STACK WITH NON-UNIFORM WIDTH
- Publication number 20050101086
- Publication date May 12, 2005
- UNITY SEMICONDUCTOR INC.
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Application
Multiple modes of operation in a cross point array
- Publication number 20050013172
- Publication date Jan 20, 2005
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Application
CONDUCTIVE MEMORY STACK WITH SIDEWALL
- Publication number 20040228172
- Publication date Nov 18, 2004
- UNITY SEMICONDUCTOR CORPORATION
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Application
LASER ANNEALING OF COMPLEX METAL OXIDES (CMO) MEMORY MATERIALS FOR...
- Publication number 20040180144
- Publication date Sep 16, 2004
- Makoto Nagashima
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Low temperature deposition of complex metal oxides (CMO) memory mat...
- Publication number 20040180542
- Publication date Sep 16, 2004
- Makoto Nagashima
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REWRITABLE MEMORY WITH NON-LINEAR MEMORY ELEMENT
- Publication number 20040170040
- Publication date Sep 2, 2004
- UNITY SEMICONDUCTOR CORPORATION
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Application
2-Terminal trapped charge memory device with voltage switchable mul...
- Publication number 20040160812
- Publication date Aug 19, 2004
- UNITY SEMICONDUCTOR CORPORATION
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Application
CROSS POINT MEMORY ARRAY USING MULTIPLE MODES OF OPERATION
- Publication number 20040160818
- Publication date Aug 19, 2004
- Unity Semiconductor Corporation
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Application
Multiplexor having a reference voltage on unselected lines
- Publication number 20040160841
- Publication date Aug 19, 2004
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-RESISTIVE STATE MATERIAL THAT USES DOPANTS
- Publication number 20040161888
- Publication date Aug 19, 2004
- UNITY SEMICONDUCTOR CORPORATION
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-LAYER CONDUCTIVE MEMORY DEVICE
- Publication number 20040159867
- Publication date Aug 19, 2004
- UNITY SEMICONDUCTOR CORPORATION
- Wayne Kinney
- G11 - INFORMATION STORAGE
Information Patent Application
Conductive memory device with barrier electrodes
- Publication number 20040159868
- Publication date Aug 19, 2004
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Application
Memory array with high temperature wiring
- Publication number 20040159869
- Publication date Aug 19, 2004
- UNITY SEMICONDUCTOR CORPORATION
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Application
Resistive memory device with a treated interface
- Publication number 20040159828
- Publication date Aug 19, 2004
- Unity Semiconductor, Inc.
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Application
Line drivers that use minimal metal layers
- Publication number 20040160846
- Publication date Aug 19, 2004
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Application
Layout of driver sets in a cross point memory array
- Publication number 20040160847
- Publication date Aug 19, 2004
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Application
Cross point memory array with fast access time
- Publication number 20040160848
- Publication date Aug 19, 2004
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARRAY OF A NON-VOLATILE RAM
- Publication number 20040160804
- Publication date Aug 19, 2004
- UNITY SEMICONDUCTOR CORPORATION
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Application
Providing a reference voltage to a cross point memory array
- Publication number 20040160806
- Publication date Aug 19, 2004
- Unity Semiconductor Corporation
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Application
Re-writable memory with multiple memory layers
- Publication number 20040160820
- Publication date Aug 19, 2004
- Darrell Rinerson
- G11 - INFORMATION STORAGE

Steve K. Hsia

Person

Patents Grantslast 30 patents

Memory element with a reactive metal layer

Memory element with a reactive metal layer

Memory element with a reactive metal layer

Memory element with a reactive metal layer

Memory element with a reactive metal layer

Memory element with a reactive metal layer

Memory element with a reactive metal layer

Memory element with a reactive metal layer

Method for fabricating multi-resistive state memory devices

Low temperature deposition of complex metal oxides (CMO) memory mat...

Virtual ground single transistor memory cell, memory array incorpor...

Cross point memory array using multiple modes of operation

Cross point memory array using distinct voltages

Multi-output multiplexor

Cross point memory array using multiple thin films

Method and apparatus for multiple byte or page mode programming of...

Method and apparatus for multiple byte or page mode programming of...

Threshold voltage convergence

Self-aligned stack formation

Low defect density composite dielectric

Memory circuit with pumped voltage for erase and program operations

Memory array architecture for flash memory

High density EEPROM cell and process for making the cell

Nonvolatile memory cell for eeprom including a floating gate to dra...

Process for making a high density split gate nonvolatile memory cell

Patents Applicationslast 30 patents

MEMORY ELEMENT WITH A REACTIVE METAL LAYER

MEMORY ELEMENT WITH A REACTIVE METAL LAYER

MEMORY ELEMENT WITH A REACTIVE METAL LAYER

MEMORY ELEMENT WITH A REACTIVE METAL LAYER

MEMORY ELEMENT WITH A REACTIVE METAL LAYER

Memory Element With a Reactive Metal Layer

Conductive memory stack with sidewall

Multi-resistive state element with reactive metal

MEMORY ELEMENT HAVING ISLANDS

Multi-resistive state element with reactive metal

CONDUCTIVE MEMORY STACK WITH NON-UNIFORM WIDTH

Multiple modes of operation in a cross point array

CONDUCTIVE MEMORY STACK WITH SIDEWALL

LASER ANNEALING OF COMPLEX METAL OXIDES (CMO) MEMORY MATERIALS FOR...

Low temperature deposition of complex metal oxides (CMO) memory mat...

REWRITABLE MEMORY WITH NON-LINEAR MEMORY ELEMENT

2-Terminal trapped charge memory device with voltage switchable mul...

CROSS POINT MEMORY ARRAY USING MULTIPLE MODES OF OPERATION

Multiplexor having a reference voltage on unselected lines

MULTI-RESISTIVE STATE MATERIAL THAT USES DOPANTS

MULTI-LAYER CONDUCTIVE MEMORY DEVICE

Conductive memory device with barrier electrodes

Memory array with high temperature wiring

Resistive memory device with a treated interface

Line drivers that use minimal metal layers

Layout of driver sets in a cross point memory array

Cross point memory array with fast access time

MEMORY ARRAY OF A NON-VOLATILE RAM

Providing a reference voltage to a cross point memory array

Re-writable memory with multiple memory layers