Claims
- 1. A non-volatile RAM memory array comprising:
a plurality of memory cells formed on a semiconductor substrate each cell capable of being selected through a select line and a data line, and having
a semiconductor device that controls current flow depending on the voltage of the select line; a multi-resistive state material that
changes its resistive state from a high resistive state to a low resistive state upon application of a first voltage pulse across the multi-resistive state material; and changes its resistive state from the low resistive state to the high resistive state upon application of a second voltage pulse across the multi-resistive state material, the second voltage pulse across the multi-resistive state material being of opposite polarity to the first voltage pulse; maintains the resistive state even if power ceases to be supplied to the memory cell, wherein
the resistive state of the memory cell determines the information stored in the memory cell; and at least one intermediary resistive state is used so that the memory cell is capable of storing more than one bit of information, whereby the multi-resistive state material is placed in the various resistive states through voltage pulses of varying magnitude, polarity, and/or duration.
- 2. The non-volatile RAM memory array of claim 1, wherein the resistive range between the high resistive state and the low resistive state is substantially evenly subdivided by the at least one intermediary resistive state.
- 3. The non-volatile RAM memory array of claim 2, wherein the intermediary resistive state logarithmically subdivides the high resistive state and the low resistive state.
- 4. A non-volatile RAM memory array that retains information in the absence of power, comprising:
a plurality of memory cells, each cell having
a multi-resistive state material that changes its resistive state between a low resistive state and a high resistive state upon application of a voltage pulse, wherein the resistive state of the memory cell determines the information stored in the memory cell; and a semiconductor device that controls current flow to the multi-resistive state material; wherein at least one intermediary resistive state is used so that the memory cell is capable of storing more than one bit of information, whereby the multi-resistive state material is placed in the various resistive states through voltage pulses of varying magnitude, polarity, and duration.
- 5. The non-volatile RAM memory of array of claim 4, wherein
at least two intermediary resistive states are used whereby the memory cell is capable of storing at least two bits of information; and the low resistive state is separated from the high resistive state by at least a factor of 10.
- 6. The non-volatile RAM memory of array of claim 5, wherein the resistive range between the high resistive state and the low resistive state is substantially evenly subdivided by the intermediary resistive states.
- 7. The non-volatile RAM memory array of claim 6, wherein the intermediary resistive state logarithmically subdivides the high resistive state and the low resistive state.
- 8. The non-volatile RAM memory of array of claim 5, wherein the multi-resistive state material is capable of changing its resistive state by at least a factor of 100 upon application of a voltage pulse.
- 9. The non-volatile RAM memory of array of claim 8, wherein the multi-resistive state material is capable of changing its resistive state by at least a factor of 1000 upon application of a voltage pulse.
- 10. The non-volatile RAM memory of array of claim 4, wherein at least six intermediary resistive states are used, whereby the memory cell is capable of storing at least three bits of information.
- 11. The non-volatile RAM memory of array of claim 10, wherein the multi-resistive state material is capable of changing its resistive state by at least a factor of 100 upon application of a voltage pulse.
- 12. The non-volatile RAM memory of array of claim 11, wherein the multi-resistive state material is capable of changing its resistive state by at least a factor of 1000 upon application of a voltage pulse.
- 13. The non-volatile RAM memory of array of claim 4, wherein at least fourteen intermediary resistive states are used, whereby the memory cell is capable of storing at least four bits of information.
- 14. The non-volatile RAM memory of array of claim 13, wherein the multi-resistive state material is capable of changing its resistive state by at least a factor of 1000 upon application of a voltage pulse.
- 15. The non-volatile RAM memory array of claim 4, wherein the low resistive state is separated from the high resistive state by at least a factor of 10.
- 16. A non-volatile RAM memory array comprising:
a plurality of memory cells formed on a semiconductor substrate, each cell capable of being selected through a select line and a data line, and having
a semiconductor device that controls current flow depending on the voltage of the select line; a first electrode layer; a multi-resistive state material layer formed on the first electrode that changes its resistive state from a high resistive state to a low resistive state upon application of a first voltage pulse across the multi-resistive state material layer; and changes its resistive state from the low resistive state to the high resistive state upon application of a second voltage pulse across the multi-resistive state material layer, the second voltage pulse across the multi-resistive state material being of opposite polarity to the first voltage pulse; maintains the resistive state even if power ceases to be supplied to the memory cell; and a second electrode layer formed on the multi-resistive state material; wherein
the resistive state of the memory cell determines the information stored in the memory cell; and each memory cell is composed of two or more active layers.
- 17. The memory plug of claim 16 wherein the first electrode and the second electrode are of different compounds.
- 18. The memory plug of claim 16 wherein the two or more active layers are the multi-resistive state material layer and at least one of the electrodes, whereby the interface of the active layers contributes to the electrical properties of the memory cell.
- 19. A memory plug comprising:
a first electrode; a multi-resistive state material formed on the first electrode that
changes its resistive state from a high resistive state to a low resistive state upon application of a first voltage pulse across the multi-resistive state material; and changes its resistive state from the low resistive state to the high resistive state upon application of a second voltage pulse across the multi-resistive state material, the second voltage pulse across the multi-resistive state material being of opposite polarity to the first voltage pulse; maintains the resistive state even if power ceases to be supplied to the memory cell; and a second electrode formed on the multi-resistive state material; wherein
the resistive state of the memory cell determines the information stored in the memory cell; and the multi-resistive state material is composed of two or more active layers.
- 20. The memory plug of claim 19 wherein the first electrode and the second electrode are of different compounds.
- 21. The memory plug of claim 19 wherein the two or more active layers are the multi-resistive state material layer and at least one of the electrodes, whereby the interface of the active layers contribute to the electrical properties of the memory cell.
- 22. A non-volatile RAM memory array comprising:
reference lines held at a constant voltage during operation; a plurality of memory cells formed on a semiconductor substrate, each memory cell having
a semiconductor device that has a first terminal and a second terminal and only allows current to flow when activated;
a first electrode layer electrically connected to the first terminal of the semiconductor device; a multi-resistive state material layer formed on the first electrode that changes its resistive state from a high resistive state to a low resistive state upon application of a first voltage pulse across the multi-resistive state material layer; changes its resistive state from the low resistive state to the high resistive state upon application of a second voltage pulse across the multi-resistive state material layer, the second voltage pulse across the multi-resistive state material being of opposite polarity to the first voltage pulse; and
maintains the resistive state even if power ceases to be supplied to the memory cell; and a second electrode layer formed on the multi-resistive state material in electrical contact with the reference line; whereby the electrodes and the multi-resistive state material are held to the voltage of the reference line when the semiconductor device is not activated.
- 23. A non-volatile RAM memory array comprising:
reference lines that are held to a constant voltage during operation; a plurality of memory cells electrically connected to the reference lines, each memory cell including
a transistor having a source, drain and gate; and a multi-resistive state material element in electrical contact with either the source or the drain of the transistor; select lines in electrical contact with the gates of the transistors; and data lines that are orthogonal to the select lines and in electrical contact with either the drains or sources of the transistors.
- 24. The memory plug of claim 23 wherein the reference lines electrically connect all of the memory cells.
- 25. A non-volatile RAM memory array comprising:
a semiconductor substrate reference lines; a plurality of memory cells electrically connected to the reference lines, each memory cell including
a transistor formed on the semiconductor; and a memory plug having a multi-resistive state material element in electrical contact with the transistor; select lines in electrical contact with the transistors; and data lines that are orthogonal to the select lines and in electrical contact with either the transistors; wherein the reference lines are parallel to the select lines and span two memory cells in the select line direction.
- 26. The non-volatile RAM memory array of claim 25 wherein the reference lines are formed on the first metalization layer above the semiconductor substrate.
- 27. The non-volatile RAM memory array of claim 26 wherein the data lines are formed on the second metalization layer above the semiconductor substrate.
- 28. The non-volatile RAM memory array of claim 28 wherein the select lines are a polysilicon material.
- 29. The non-volatile RAM memory array of claim 28 wherein the multi-resistive state material is a complex metal oxide.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of U.S. Provisional Application No. 60/400,849, filed Aug. 2, 2002, and the U.S. Provisional Application No. 60/422,922, filed Oct. 31, 2002, both of which are incorporated herein by reference in their entireties and for all purposes. This application is related to the following U.S. patent applications: U.S. application Ser. No. 10/360,005, filed Feb. 7, 2003; U.S. application Ser. No. 10/330,512, filed Dec. 26, 2002; application Ser. No. 10/330,153, filed Dec. 26, 2002; application Ser. No. 10/330,964, filed Dec. 26, 2002; application Ser. No. 10/330,170, filed Dec. 26, 2002; application Ser. No. 10/330,900, filed Dec. 26, 2002; application Ser. No. 10/330,150, filed Dec. 26, 2002; and application Ser. No. 10/330,965, filed Dec. 26, 2002; all of which are hereby incorporated herein by reference in their entireties and for all purposes. This application is additionally related to the U.S. Patent Applications titled “Non-Volatile Memory With A Single Transistor And Resistive Memory Element” filed on date even herewith, hereby incorporated herein by reference in its entirety and for all purposes.
Provisional Applications (2)
|
Number |
Date |
Country |
|
60400849 |
Aug 2002 |
US |
|
60422922 |
Oct 2002 |
US |