Subhash R. Nariani

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Anti-fuse structure for reducing contamination of the anti-fuse mat...
- Patent number RE36893
- Issue date Oct 3, 2000
- VLSI Technology, Inc.
- Dipankar Pramanik
- 257 - Active solid-state devices
Information Patent Grant
Dual gate oxide process with increased reliability
- Patent number 6,015,732
- Issue date Jan 18, 2000
- VLSI Technology, Inc.
- Jon Roderick Williamson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device reliability of MOS devices using silicon rich plasma oxide f...
- Patent number 5,763,937
- Issue date Jun 9, 1998
- VLSI Technology, Inc.
- Vivek Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for wafer level prediction of thin oxide relia...
- Patent number 5,638,006
- Issue date Jun 10, 1997
- VLSI Technology, Inc.
- Subhash R. Nariani
- G01 - MEASURING TESTING
Information Patent Grant
Method for forming reliable MOS devices using silicon rich plasma o...
- Patent number 5,602,056
- Issue date Feb 11, 1997
- VLSI Technology, Inc.
- Vivek Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making flash memory cell
- Patent number 5,587,332
- Issue date Dec 24, 1996
- VLSI Technology, Inc.
- Kuang-Yeh Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for reducing contamination of anti-fuse material in an anti-...
- Patent number 5,573,970
- Issue date Nov 12, 1996
- VLSI Technology, Inc.
- Dipankar Pramanik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for wafer level prediction of thin oxide relia...
- Patent number 5,548,224
- Issue date Aug 20, 1996
- VLSI Technology, Inc.
- Calvin T. Gabriel
- G01 - MEASURING TESTING
Information Patent Grant
Anti-fuse structure for reducing contamination of the anti-fuse mat...
- Patent number 5,493,146
- Issue date Feb 20, 1996
- VLSI Technology, Inc.
- Dipankar Pramanik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making structure for suppression of field inversion cause...
- Patent number 5,492,865
- Issue date Feb 20, 1996
- VLSI Technology, Inc.
- Subhash R. Nariani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a polysilicon-on-silicide capacitor
- Patent number 5,470,775
- Issue date Nov 28, 1995
- VLSI Technology, Inc.
- Subhash R. Nariani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure for suppression of field inversion caused by charge build...
- Patent number 5,374,833
- Issue date Dec 20, 1994
- VLSI Technology, Inc.
- Subhash R. Nariani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
EEPROM cell with improved tunneling properties
- Patent number 5,371,393
- Issue date Dec 6, 1994
- VLSI Technology, Inc.
- Kuang-Yeh Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making cusp-free anti-fuse structures
- Patent number 5,328,865
- Issue date Jul 12, 1994
- VLSI Technology, Inc.
- William J. Boardman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making anti-fuse structures
- Patent number 5,290,734
- Issue date Mar 1, 1994
- VLSI Technology, Inc.
- William J. Boardman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for suppressing charge loss in EEPROMs/EPROMS and instabilit...
- Patent number 5,290,727
- Issue date Mar 1, 1994
- VLSI Technology, Inc.
- Vivek Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Inter-silicide capacitor
- Patent number 5,218,511
- Issue date Jun 8, 1993
- VLSI Technology, Inc.
- Subhash R. Nariani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making an E.sup.2 PROM cell with improved tunneling prope...
- Patent number 5,198,381
- Issue date Mar 30, 1993
- VLSI Technology, Inc.
- Kuang-Yeh Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Charge neutralization using silicon-enriched oxide layer
- Patent number 5,128,279
- Issue date Jul 7, 1992
- VLSI Technology, Inc.
- Subhash R. Nariani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Anti-fuse structures and methods for making same
- Patent number 5,120,679
- Issue date Jun 9, 1992
- VLSI Technology, Inc.
- William J. Boardman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Charge neutralization using silicon-enriched oxide layer
- Patent number 5,057,897
- Issue date Oct 15, 1991
- VLSI Technology, Inc.
- Subhash R. Nariani
- H01 - BASIC ELECTRIC ELEMENTS

Subhash R. Nariani

Person

Patents Grantslast 30 patents

Anti-fuse structure for reducing contamination of the anti-fuse mat...

Dual gate oxide process with increased reliability

Device reliability of MOS devices using silicon rich plasma oxide f...

Method and apparatus for wafer level prediction of thin oxide relia...

Method for forming reliable MOS devices using silicon rich plasma o...

Method of making flash memory cell

Method for reducing contamination of anti-fuse material in an anti-...

Method and apparatus for wafer level prediction of thin oxide relia...

Anti-fuse structure for reducing contamination of the anti-fuse mat...

Method of making structure for suppression of field inversion cause...

Method of forming a polysilicon-on-silicide capacitor

Structure for suppression of field inversion caused by charge build...

EEPROM cell with improved tunneling properties

Method for making cusp-free anti-fuse structures

Method for making anti-fuse structures

Method for suppressing charge loss in EEPROMs/EPROMS and instabilit...

Inter-silicide capacitor

Method of making an E.sup.2 PROM cell with improved tunneling prope...

Charge neutralization using silicon-enriched oxide layer

Anti-fuse structures and methods for making same

Charge neutralization using silicon-enriched oxide layer