Subramanian Ramesh

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Basic cell architecture for structured ASICs
- Patent number 8,429,586
- Issue date Apr 23, 2013
- LSI Corporation
- Ramnath Venkatraman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit cell architecture configurable for memory or log...
- Patent number 8,178,909
- Issue date May 15, 2012
- LSI Corporation
- Ramnath Venkatraman
- G11 - INFORMATION STORAGE
Information Patent Grant
Basic cell architecture for structured application-specific integra...
- Patent number 8,166,440
- Issue date Apr 24, 2012
- LSI Corporation
- Ramnath Venkatraman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit cell architecture configurable for memory or log...
- Patent number 8,044,437
- Issue date Oct 25, 2011
- LSI Logic Corporation
- Ramnath Venkatraman
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM based one-time-programmable memory
- Patent number 7,869,251
- Issue date Jan 11, 2011
- LSI Corporation
- Ramnath Venkatraman
- G11 - INFORMATION STORAGE
Information Patent Grant
Modular design of multiport memory bitcells
- Patent number 7,440,356
- Issue date Oct 21, 2008
- LSI Corporation
- Ramnath Venkatraman
- G11 - INFORMATION STORAGE
Information Patent Grant
Basic cell architecture for structured application-specific integra...
- Patent number 7,404,154
- Issue date Jul 22, 2008
- LSI Corporation
- Ramnath Venkatraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory cell architecture
- Patent number 7,006,370
- Issue date Feb 28, 2006
- LSI Logic Corporation
- Subramanian Ramesh
- G11 - INFORMATION STORAGE
Information Patent Grant
Design and use of a spacer cell to support reconfigurable memories
- Patent number 7,006,369
- Issue date Feb 28, 2006
- LSI Logic Corporation
- Ramnath Venkatraman
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell architecture for reduced routing congestion
- Patent number 6,980,462
- Issue date Dec 27, 2005
- LSI Logic Corporation
- Subramanian Ramesh
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and architecture for detecting random and systematic transis...
- Patent number 6,978,407
- Issue date Dec 20, 2005
- LSI Logic Corporation
- Franklin L. Duan
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for characterizing shared contacts in high-den...
- Patent number 6,977,512
- Issue date Dec 20, 2005
- LSI Logic Corporation
- Franklin Duan
- G11 - INFORMATION STORAGE
Information Patent Grant
Reconfigurable memory arrays
- Patent number 6,934,174
- Issue date Aug 23, 2005
- LSI Logic Corporation
- Ruggero Castagnetti
- G11 - INFORMATION STORAGE
Information Patent Grant
Metal-programmable single-port SRAM array for dual-port functionality
- Patent number 6,778,462
- Issue date Aug 17, 2004
- LSI Logic Corporation
- Ruggero Castagnetti
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-aligned fuse structure and method with dual-thickness dielectric
- Patent number 6,413,848
- Issue date Jul 2, 2002
- LSI Logic Corporation
- Gary K. Giust
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned fuse structure and method with heat sink
- Patent number 6,259,146
- Issue date Jul 10, 2001
- LSI Logic Corporation
- Gary K. Giust
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicide encapsulation of polysilicon gate and interconnect
- Patent number 6,218,276
- Issue date Apr 17, 2001
- LSI Logic Corporation
- Yauh-Ching Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit having embedded memory with electromagnetic shield
- Patent number 6,166,403
- Issue date Dec 26, 2000
- LSI Logic Corporation
- Ruggero Castagnetti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming thin polygates for sub quarter micron CMOS process
- Patent number 6,162,714
- Issue date Dec 19, 2000
- LSI Logic Corporation
- Ruggero Castagnetti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming DRAM capacitor by forming separate dielectric lay...
- Patent number 6,066,525
- Issue date May 23, 2000
- LSI Logic Corporation
- Yauh-Ching Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned fuse structure and method with anti-reflective coating
- Patent number 6,061,264
- Issue date May 9, 2000
- LSI Logic Corporation
- Gary K. Giust
- G11 - INFORMATION STORAGE
Information Patent Grant
Metal-encapsulated polysilicon gate and interconnect
- Patent number 6,037,233
- Issue date Mar 14, 2000
- LSI Logic Corporation
- Yauh-Ching Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming self-aligned metal silicide contacts for MOS st...
- Patent number 5,953,614
- Issue date Sep 14, 1999
- LSI Logic Corporation
- Yauh-Ching Liu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Basic Cell Architecture For Structured ASICs
- Publication number 20120175683
- Publication date Jul 12, 2012
- LSI Corporation
- Ramnath Venkatraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated Circuit Cell Architecture Configurable for Memory or Log...
- Publication number 20120012896
- Publication date Jan 19, 2012
- Ramnath Venkatraman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SRAM BASED ONE-TIME-PROGRAMMABLE MEMORY
- Publication number 20100080035
- Publication date Apr 1, 2010
- Ramnath Venkatraman
- G11 - INFORMATION STORAGE
Information Patent Application
Modular design of multiport memory bitcells
- Publication number 20080013383
- Publication date Jan 17, 2008
- LSI Logic Corporation
- Ramnath Venkatraman
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for characterizing shared contacts in high-den...
- Publication number 20050122120
- Publication date Jun 9, 2005
- Franklin Duan
- G11 - INFORMATION STORAGE
Information Patent Application
Reconfigurable memory arrays
- Publication number 20050047238
- Publication date Mar 3, 2005
- Ruggero Castagnetti
- G11 - INFORMATION STORAGE
Information Patent Application
Design and use of a spacer cell to support reconfigurable memories
- Publication number 20050047254
- Publication date Mar 3, 2005
- Ramnath Venkatraman
- G11 - INFORMATION STORAGE
Information Patent Application
Method and architecture for detecting random and systematic transis...
- Publication number 20040243890
- Publication date Dec 2, 2004
- Franklin L. Duan
- G11 - INFORMATION STORAGE

Subramanian Ramesh

Person

Patents Grantslast 30 patents

Basic cell architecture for structured ASICs

Integrated circuit cell architecture configurable for memory or log...

Basic cell architecture for structured application-specific integra...

Integrated circuit cell architecture configurable for memory or log...

SRAM based one-time-programmable memory

Modular design of multiport memory bitcells

Basic cell architecture for structured application-specific integra...

Memory cell architecture

Design and use of a spacer cell to support reconfigurable memories

Memory cell architecture for reduced routing congestion

Method and architecture for detecting random and systematic transis...

Method and apparatus for characterizing shared contacts in high-den...

Reconfigurable memory arrays

Metal-programmable single-port SRAM array for dual-port functionality

Self-aligned fuse structure and method with dual-thickness dielectric

Self-aligned fuse structure and method with heat sink

Silicide encapsulation of polysilicon gate and interconnect

Integrated circuit having embedded memory with electromagnetic shield

Method of forming thin polygates for sub quarter micron CMOS process

Method of forming DRAM capacitor by forming separate dielectric lay...

Self-aligned fuse structure and method with anti-reflective coating

Metal-encapsulated polysilicon gate and interconnect

Process for forming self-aligned metal silicide contacts for MOS st...

Patents Applicationslast 30 patents

Basic Cell Architecture For Structured ASICs

Integrated Circuit Cell Architecture Configurable for Memory or Log...

SRAM BASED ONE-TIME-PROGRAMMABLE MEMORY

Modular design of multiport memory bitcells

Method and apparatus for characterizing shared contacts in high-den...

Reconfigurable memory arrays

Design and use of a spacer cell to support reconfigurable memories

Method and architecture for detecting random and systematic transis...