Suebphong Yenrudee

Person

Bangkok, TH

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor package with multiple molding routing layers and a me...
- Patent number 10,734,247
- Issue date Aug 4, 2020
- UTAC HEADQUARTERS PTE. LTD.
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with plated metal shielding and a method thereof
- Patent number 10,600,741
- Issue date Mar 24, 2020
- UTAC HEADQUARTERS PTE. LTD.
- Suebphong Yenrudee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with multiple stacked leadframes and a method...
- Patent number 10,361,146
- Issue date Jul 23, 2019
- UTAC HEADQUARTERS PTE, LTD.
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with multiple molding routing layers and a me...
- Patent number 10,325,782
- Issue date Jun 18, 2019
- UTAC HEADQUARTERS PTE. LTD.
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with multiple stacked leadframes and a method...
- Patent number 10,276,477
- Issue date Apr 30, 2019
- UTAC HEADQUARTERS PTE. LTD.
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of improving adhesion between molding compounds and an appar...
- Patent number 10,269,686
- Issue date Apr 23, 2019
- UTAC HEADQUARTERS PTE, LTD.
- Suebphong Yenrudee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with plated metal shielding and a method thereof
- Patent number 10,242,953
- Issue date Mar 26, 2019
- UTAC HEADQUARTERS PTE. LTD.
- Suebphong Yenrudee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with multiple molding routing layers and a me...
- Patent number 10,163,658
- Issue date Dec 25, 2018
- UTAC HEADQUARTERS PTE, LTD.
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with multiple molding routing layers and a me...
- Patent number 10,096,490
- Issue date Oct 9, 2018
- UTAC HEADQUARTERS PTE. LTD.
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with multiple molding routing layers and a me...
- Patent number 10,032,645
- Issue date Jul 24, 2018
- UTAC HEADQUARTERS PTE. LTD.
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with multiple molding routing layers and a me...
- Patent number 9,922,843
- Issue date Mar 20, 2018
- UTAC HEADQUARTERS PTE. LTD.
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with multiple molding routing layers and a me...
- Patent number 9,917,038
- Issue date Mar 13, 2018
- UTAC HEADQUARTERS PTE. LTD.
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with multiple molding routing layers and a me...
- Patent number 9,805,955
- Issue date Oct 31, 2017
- UTAC HEADQUARTERS PTE. LTD.
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Leadframe feature to minimize flip-chip semiconductor die collapse...
- Patent number 9,449,900
- Issue date Sep 20, 2016
- UTAC HEADQUARTERS PTE. LTD.
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of manufacturing semiconductor devices including terminals...
- Patent number 9,029,198
- Issue date May 12, 2015
- UTAC Thai Limited
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Protruding terminals with internal routing interconnections semicon...
- Patent number 9,000,590
- Issue date Apr 7, 2015
- UTAC Thai Limited
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR PACKAGE WITH MULTIPLE STACKED LEADFRAMES AND A METHOD...
- Publication number 20190181077
- Publication date Jun 13, 2019
- UTAC Headquarters Pte. Ltd.
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE WITH MULTIPLE MOLDING ROUTING LAYERS AND A ME...
- Publication number 20180061667
- Publication date Mar 1, 2018
- UTAC Headquarters Pte. Ltd.
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE WITH MULTIPLE MOLDING ROUTING LAYERS AND A ME...
- Publication number 20170352554
- Publication date Dec 7, 2017
- UTAC Headquarters Pte. Ltd.
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE WITH MULTIPLE MOLDING ROUTING LAYERS AND A ME...
- Publication number 20170352555
- Publication date Dec 7, 2017
- UTAC Headquarters Pte. Ltd.
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE WITH MULTIPLE MOLDING ROUTING LAYERS AND A ME...
- Publication number 20170352610
- Publication date Dec 7, 2017
- UTAC Headquarters Pte. Ltd.
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING TERMINALS...
- Publication number 20130302944
- Publication date Nov 14, 2013
- UTAC Thai Limited
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROTRUDING TERMINALS WITH INTERNAL ROUTING INTERCONNECTIONS SEMICON...
- Publication number 20130299980
- Publication date Nov 14, 2013
- UTAC Thai Limited
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LEADFRAME FEATURE TO MINIMIZE FLIP-CHIP SEMICONDUCTOR DIE COLLAPSE...
- Publication number 20110018111
- Publication date Jan 27, 2011
- UTAC Thai Limited
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS

Suebphong Yenrudee

Person

Patents Grantslast 30 patents

Semiconductor package with multiple molding routing layers and a me...

Semiconductor package with plated metal shielding and a method thereof

Semiconductor package with multiple stacked leadframes and a method...

Semiconductor package with multiple molding routing layers and a me...

Semiconductor package with multiple stacked leadframes and a method...

Method of improving adhesion between molding compounds and an appar...

Semiconductor package with plated metal shielding and a method thereof

Semiconductor package with multiple molding routing layers and a me...

Semiconductor package with multiple molding routing layers and a me...

Semiconductor package with multiple molding routing layers and a me...

Semiconductor package with multiple molding routing layers and a me...

Semiconductor package with multiple molding routing layers and a me...

Semiconductor package with multiple molding routing layers and a me...

Leadframe feature to minimize flip-chip semiconductor die collapse...

Methods of manufacturing semiconductor devices including terminals...

Protruding terminals with internal routing interconnections semicon...

Patents Applicationslast 30 patents

SEMICONDUCTOR PACKAGE WITH MULTIPLE STACKED LEADFRAMES AND A METHOD...

SEMICONDUCTOR PACKAGE WITH MULTIPLE MOLDING ROUTING LAYERS AND A ME...

SEMICONDUCTOR PACKAGE WITH MULTIPLE MOLDING ROUTING LAYERS AND A ME...

SEMICONDUCTOR PACKAGE WITH MULTIPLE MOLDING ROUTING LAYERS AND A ME...

SEMICONDUCTOR PACKAGE WITH MULTIPLE MOLDING ROUTING LAYERS AND A ME...

METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING TERMINALS...

PROTRUDING TERMINALS WITH INTERNAL ROUTING INTERCONNECTIONS SEMICON...

LEADFRAME FEATURE TO MINIMIZE FLIP-CHIP SEMICONDUCTOR DIE COLLAPSE...