Sung-Wei Lin

Person

Plano, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
System and method for reading memory
- Patent number 7,813,198
- Issue date Oct 12, 2010
- Texas Instruments Incorporated
- Sung-Wei Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and systems for accessing memory
- Patent number 7,630,257
- Issue date Dec 8, 2009
- Texas Instruments Incorporated
- Sudhir Kumar Madan
- G11 - INFORMATION STORAGE
Information Patent Grant
Active float for the dummy bit lines in FeRAM
- Patent number 7,463,504
- Issue date Dec 9, 2008
- Texas Instruments Incorporated
- Sung-Wei Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Low resistance plate line bus architecture
- Patent number 7,443,708
- Issue date Oct 28, 2008
- Texas Instruments Incorporated
- Sudhir Kumar Madan
- G11 - INFORMATION STORAGE
Information Patent Grant
Plateline driver with RAMP rate control
- Patent number 7,349,237
- Issue date Mar 25, 2008
- Texas Instruments Incorporated
- Sung-Wei Lin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Accelerated low power fatigue testing of FRAM
- Patent number 7,301,795
- Issue date Nov 27, 2007
- Texas Instruments Incorporated
- John Y. Fong
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus to reduce storage node disturbance in ferroele...
- Patent number 7,133,304
- Issue date Nov 7, 2006
- Texas Instruments Incorporated
- Sudhir Kumar Madan
- G11 - INFORMATION STORAGE
Information Patent Grant
Temperature and supply-voltage sensing circuit
- Patent number 5,694,073
- Issue date Dec 2, 1997
- Texas Instruments Incorporated
- Timothy J. Coots
- G05 - CONTROLLING REGULATING
Information Patent Grant
Memory device performance by delayed power-down
- Patent number 5,668,769
- Issue date Sep 16, 1997
- Texas Instruments Incorporated
- Tim M. Coffman
- G11 - INFORMATION STORAGE
Information Patent Grant
Array-source line, bitline and wordline sequence in flash operations
- Patent number 5,657,268
- Issue date Aug 12, 1997
- Texas Instruments Incorporated
- Phat C. Truong
- G11 - INFORMATION STORAGE
Information Patent Grant
Smart boost circuit for low voltage flash EPROM
- Patent number 5,646,894
- Issue date Jul 8, 1997
- Texas Instruments Incorporated
- Sung-Wei Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Erase procedure
- Patent number 5,636,162
- Issue date Jun 3, 1997
- Texas Instruments Incorporated
- Tim M. Coffman
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of making an EEPROM cell with separate erasing and programmi...
- Patent number 5,523,249
- Issue date Jun 4, 1996
- Texas Instruments Incorporated
- Manzur Gill
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Smart erase algorithm with secure scheme for flash EPROMs
- Patent number 5,491,809
- Issue date Feb 13, 1996
- Texas Instruments Incorporated
- Tim M. Coffman
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit for testing power-on-reset circuitry
- Patent number 5,450,417
- Issue date Sep 12, 1995
- Texas Instruments Incorporated
- Phat C. Truong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and device for detecting and controlling an array source sig...
- Patent number 5,424,992
- Issue date Jun 13, 1995
- Texas Instruments Incorporated, a Delaware corporation
- Tim M. Coffman
- G11 - INFORMATION STORAGE
Information Patent Grant
High voltage negative charge pump with low voltage CMOS transistors
- Patent number 5,422,590
- Issue date Jun 6, 1995
- Texas Instruments Incorporated
- Tim M. Coffman
- G11 - INFORMATION STORAGE
Information Patent Grant
High-voltage sensor for integrated circuits
- Patent number 5,397,946
- Issue date Mar 14, 1995
- Texas Instruments Incorporated
- Phat C. Truong
- G11 - INFORMATION STORAGE
Information Patent Grant
Current-sensing power-on reset circuit for integrated circuits
- Patent number 5,396,115
- Issue date Mar 7, 1995
- Texas Instruments Incorporated
- Tim M. Coffman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit and method for detecting column-line shorts in integrated-c...
- Patent number 5,392,248
- Issue date Feb 21, 1995
- Texas Instruments Incorporated
- Phat C. Truong
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of producing a self-aligned window at recessed intersection...
- Patent number 5,334,550
- Issue date Aug 2, 1994
- Texas Instruments Incorporated
- David J. McElroy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High voltage negative charge pump with low voltage CMOS transistors
- Patent number 5,335,200
- Issue date Aug 2, 1994
- Texas Instruments Incorporated
- Tim M. Coffman
- G11 - INFORMATION STORAGE
Information Patent Grant
Segmented, multiple-decoder memory array and method for programming...
- Patent number 5,313,432
- Issue date May 17, 1994
- Texas Instruments Incorporated
- Sung-Wei Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Wordline driver circuit for EEPROM memory cell
- Patent number 5,265,052
- Issue date Nov 23, 1993
- Texas Instruments Incorporated
- Sebastiano D'Arrigo
- G11 - INFORMATION STORAGE
Information Patent Grant
Electrically-erasable, electrically-programmable read-only memory c...
- Patent number 5,218,568
- Issue date Jun 8, 1993
- Texas Instruments Incorporated
- Sung-Wei Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for programming EEPROM memory arrays
- Patent number 5,187,683
- Issue date Feb 16, 1993
- Texas Instruments Incorporated
- Manzur Gill
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming of an electrically-erasable, electrically-programmable,...
- Patent number 5,177,705
- Issue date Jan 5, 1993
- Texas Instruments Incorporated
- David J. McElroy
- G11 - INFORMATION STORAGE
Information Patent Grant
Electrically programmable, electrically erasable memory array cell...
- Patent number 5,168,335
- Issue date Dec 1, 1992
- Texas Instruments Incorporated
- Iano D'Arrigo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabricating an electrically-erasable, electrically-programmable rea...
- Patent number 5,156,991
- Issue date Oct 20, 1992
- Texas Instruments Incorporated
- Manzur Gill
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making an electrically-erasable, electrically-programmabl...
- Patent number 5,155,055
- Issue date Oct 13, 1992
- Texas Instruments Incorporated
- Manzur Gill
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD FOR READING MEMORY
- Publication number 20090034338
- Publication date Feb 5, 2009
- Sung-Wei Lin
- G11 - INFORMATION STORAGE
Information Patent Application
LOW RESISTANCE PLATE LINE BUS ARCHITECTURE
- Publication number 20090010038
- Publication date Jan 8, 2009
- TEXAS INSTRUMENTS INCORPORATED
- SUDHIR KUMAR MADAN
- G11 - INFORMATION STORAGE
Information Patent Application
Methods and systems for accessing memory
- Publication number 20080084773
- Publication date Apr 10, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Sudhir Kumar Madan
- G11 - INFORMATION STORAGE
Information Patent Application
Plateline Driver with Ramp Rate Control
- Publication number 20080079471
- Publication date Apr 3, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Sung-Wei Lin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low resistance plate line bus architecture
- Publication number 20070211510
- Publication date Sep 13, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Sudhir Kumar Madan
- G11 - INFORMATION STORAGE
Information Patent Application
Active float for the dummy bit lines in FeRAM
- Publication number 20070058413
- Publication date Mar 15, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Sung-Wei Lin
- G11 - INFORMATION STORAGE
Information Patent Application
High granularity redundancy for ferroelectric memories
- Publication number 20070038805
- Publication date Feb 15, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Jarrod Randall Eliason
- G11 - INFORMATION STORAGE
Information Patent Application
Accelerated low power fatigue testing of fram
- Publication number 20060107095
- Publication date May 18, 2006
- TEXAS INSTRUMENTS INCORPORATED
- John Y. Fong
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus to reduce storage node disturbance in ferroele...
- Publication number 20050207201
- Publication date Sep 22, 2005
- Sudhir Kumar Madan
- G11 - INFORMATION STORAGE
Information Patent Application
Plateline driver with RAMP rate control
- Publication number 20050078504
- Publication date Apr 14, 2005
- Sung-Wei Lin
- H03 - BASIC ELECTRONIC CIRCUITRY

Sung-Wei Lin

Person

Patents Grantslast 30 patents

System and method for reading memory

Methods and systems for accessing memory

Active float for the dummy bit lines in FeRAM

Low resistance plate line bus architecture

Plateline driver with RAMP rate control

Accelerated low power fatigue testing of FRAM

Method and apparatus to reduce storage node disturbance in ferroele...

Temperature and supply-voltage sensing circuit

Memory device performance by delayed power-down

Array-source line, bitline and wordline sequence in flash operations

Smart boost circuit for low voltage flash EPROM

Erase procedure

Method of making an EEPROM cell with separate erasing and programmi...

Smart erase algorithm with secure scheme for flash EPROMs

Circuit for testing power-on-reset circuitry

Method and device for detecting and controlling an array source sig...

High voltage negative charge pump with low voltage CMOS transistors

High-voltage sensor for integrated circuits

Current-sensing power-on reset circuit for integrated circuits

Circuit and method for detecting column-line shorts in integrated-c...

Method of producing a self-aligned window at recessed intersection...

High voltage negative charge pump with low voltage CMOS transistors

Segmented, multiple-decoder memory array and method for programming...

Wordline driver circuit for EEPROM memory cell

Electrically-erasable, electrically-programmable read-only memory c...

Method for programming EEPROM memory arrays

Programming of an electrically-erasable, electrically-programmable,...

Electrically programmable, electrically erasable memory array cell...

Fabricating an electrically-erasable, electrically-programmable rea...

Method of making an electrically-erasable, electrically-programmabl...

Patents Applicationslast 30 patents

SYSTEM AND METHOD FOR READING MEMORY

LOW RESISTANCE PLATE LINE BUS ARCHITECTURE

Methods and systems for accessing memory

Plateline Driver with Ramp Rate Control

Low resistance plate line bus architecture

Active float for the dummy bit lines in FeRAM

High granularity redundancy for ferroelectric memories

Accelerated low power fatigue testing of fram

Method and apparatus to reduce storage node disturbance in ferroele...

Plateline driver with RAMP rate control