Suraj Kumar Patil

Person

East Fishkill, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integration scheme for gate height control and void free RMG fill
- Patent number 10,354,928
- Issue date Jul 16, 2019
- GLOBALFOUNDRIES Inc.
- Suraj Kumar Patil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Heterogeneous integration of 3D SI and III-V vertical nanowire stru...
- Patent number 10,319,642
- Issue date Jun 11, 2019
- GLOBALFOUNDRIES Inc.
- Suraj Kumar Patil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integration of gate structures and spacers with air gaps
- Patent number 10,236,358
- Issue date Mar 19, 2019
- GLOBALFOUNDRIES Inc.
- Suraj K. Patil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integration scheme for gate height control and void free RMG fill
- Patent number 10,056,303
- Issue date Aug 21, 2018
- GLOBALFOUNDRIES Inc.
- Suraj Kumar Patil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable via devices with metal/semiconductor via links and fab...
- Patent number 10,056,331
- Issue date Aug 21, 2018
- GLOBALFOUNDRIES Inc.
- Ajey P. Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method for capping cobalt contacts
- Patent number 10,043,708
- Issue date Aug 7, 2018
- GLOBALFOUNDRIES Inc.
- Viraj Sardesai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming MIS contact structures on transistor devices
- Patent number 9,831,123
- Issue date Nov 28, 2017
- GLOBALFOUNDRIES Inc.
- Suraj K. Patil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method, apparatus, and system for E-fuse in advanced CMOS technologies
- Patent number 9,831,175
- Issue date Nov 28, 2017
- GLOBALFOUNDRIES Inc.
- Suraj Kumar Patil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable via devices with metal/semiconductor via links and fab...
- Patent number 9,812,393
- Issue date Nov 7, 2017
- GLOBALFOUNDRIES Inc.
- Ajey P. Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Heterogeneous integration of 3D Si and III-V vertical nanowire stru...
- Patent number 9,754,843
- Issue date Sep 5, 2017
- GLOBALFOUNDRIES Inc.
- Suraj Kumar Patil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with anti-efuse device
- Patent number 9,754,903
- Issue date Sep 5, 2017
- GLOBALFOUNDRIES INC.
- Suraj K. Patil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuits with replacement metal gates and methods for fa...
- Patent number 9,698,241
- Issue date Jul 4, 2017
- GLOBALFOUNDRIES, INC.
- Suraj K. Patil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable devices with current-facilitated migration and fabrica...
- Patent number 9,691,497
- Issue date Jun 27, 2017
- GLOBALFOUNDRIES Inc.
- Suraj K. Patil
- G11 - INFORMATION STORAGE
Information Patent Grant
Method, apparatus, and system for e-fuse in advanced CMOS technologies
- Patent number 9,659,862
- Issue date May 23, 2017
- GLOBALFOUNDRIES Inc.
- Suraj Kumar Patil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Facilitating etch processing of a thin film via partial implantatio...
- Patent number 9,620,381
- Issue date Apr 11, 2017
- GLOBALFOUNDRIES Inc.
- Suraj K. Patil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming MIS contact structures on transistor devices in...
- Patent number 9,613,855
- Issue date Apr 4, 2017
- GLOBALFOUNDRIES Inc.
- Suraj K. Patil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Inline buried metal void detection by surface plasmon resonance (SPR)
- Patent number 9,588,044
- Issue date Mar 7, 2017
- GLOBALFOUNDRIES Inc.
- Sabarinath Jayaseelan
- G01 - MEASURING TESTING
Information Patent Grant
Multiple layer interface formation for semiconductor structure
- Patent number 9,570,572
- Issue date Feb 14, 2017
- GLOBALFOUNDRIES Inc.
- Suraj K. Patil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for fabricating programmable devices and related structures
- Patent number 9,564,447
- Issue date Feb 7, 2017
- GLOBALFOUNDRIES Inc.
- Suraj K. Patil
- G11 - INFORMATION STORAGE
Information Patent Grant
Fabrication methods for multi-layer semiconductor structures
- Patent number 9,502,301
- Issue date Nov 22, 2016
- GLOBALFOUNDRIES Inc.
- Suraj K. Patil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
MOL contact metallization scheme for improved yield and device reli...
- Patent number 9,396,995
- Issue date Jul 19, 2016
- GLOBALFOUNDRIES Inc.
- Suraj K. Patil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Mask structures and methods of manufacturing
- Patent number 9,195,132
- Issue date Nov 24, 2015
- Globalfoundries Inc.
- Suraj K. Patil
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method and apparatus for fabricating piezoresistive polysilicon by...
- Patent number 9,006,016
- Issue date Apr 14, 2015
- Board of Regents, The University of Texas System
- Zeynep Celik-Butler
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for fabricating piezoresistive polysilicon by...
- Patent number 8,492,238
- Issue date Jul 23, 2013
- Board of Regents, The University of Texas System
- Zeynep Celik-Butler
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
METHODS FOR FORMING IC STRUCTURE HAVING RECESSED GATE SPACERS AND R...
- Publication number 20190131424
- Publication date May 2, 2019
- GLOBALFOUNDRIES INC.
- Guowei Xu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE STACK PROCESSES AND STRUCTURES
- Publication number 20190096679
- Publication date Mar 28, 2019
- GLOBALFOUNDRIES INC.
- Balaji Kannan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATION SCHEME FOR GATE HEIGHT CONTROL AND VOID FREE RMG FILL
- Publication number 20180323113
- Publication date Nov 8, 2018
- GLOBALFOUNDRIES INC.
- Suraj Kumar PATIL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD FOR CAPPING COBALT CONTACTS
- Publication number 20180277427
- Publication date Sep 27, 2018
- GLOBALFOUNDRIES INC.
- Viraj SARDESAI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENCAPSULATION OF COBALT METALLIZATION
- Publication number 20180130702
- Publication date May 10, 2018
- GLOBALFOUNDRIES INC.
- Suraj K. Patil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD FOR CAPPING COBALT CONTACTS
- Publication number 20180130703
- Publication date May 10, 2018
- Viraj SARDESAI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROGRAMMABLE VIA DEVICES WITH METAL/SEMICONDUCTOR VIA LINKS AND FAB...
- Publication number 20180033726
- Publication date Feb 1, 2018
- GLOBALFOUNDRIES INC.
- Ajey P. JACOB
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECTS WITH INNER SACRIFICIAL SPACERS
- Publication number 20180012791
- Publication date Jan 11, 2018
- GLOBALFOUNDRIES Inc.
- Zhiguo Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HETEROGENEOUS INTEGRATION OF 3D SI AND III-V VERTICAL NANOWIRE STRU...
- Publication number 20180012812
- Publication date Jan 11, 2018
- GLOBALFOUNDRIES INC.
- Suraj Kumar PATIL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING MIS CONTACT STRUCTURES ON TRANSISTOR DEVICES
- Publication number 20170287777
- Publication date Oct 5, 2017
- GLOBALFOUNDRIES INC.
- Suraj K. Patil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD, APPARATUS, AND SYSTEM FOR E-FUSE IN ADVANCED CMOS TECHNOLOGIES
- Publication number 20170221823
- Publication date Aug 3, 2017
- Suraj Kumar Patil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ON-CHIP VARIABLE CAPACITOR WITH GEOMETRIC CROSS-SECTION
- Publication number 20170194245
- Publication date Jul 6, 2017
- GLOBALFOUNDRIES INC.
- Suraj PATIL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD, APPARATUS, AND SYSTEM FOR E-FUSE IN ADVANCED CMOS TECHNOLOGIES
- Publication number 20170133319
- Publication date May 11, 2017
- GLOBALFOUNDRIES INC.
- Suraj Kumar Patil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE WITH ANTI-EFUSE DEVICE
- Publication number 20170125361
- Publication date May 4, 2017
- GLOBALFOUNDRIES INC.
- Suraj K. PATIL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROGRAMMABLE DEVICES WITH CURRENT-FACILITATED MIGRATION AND FABRICA...
- Publication number 20170092373
- Publication date Mar 30, 2017
- GLOBALFOUNDRIES INC.
- Suraj K. PATIL
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMABLE VIA DEVICES WITH METAL/SEMICONDUCTOR VIA LINKS AND FAB...
- Publication number 20170092583
- Publication date Mar 30, 2017
- GLOBALFOUNDRIES INC.
- Ajey P. JACOB
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FABRICATING PROGRAMMABLE DEVICES AND RELATED STRUCTURES
- Publication number 20170062442
- Publication date Mar 2, 2017
- GLOBALFOUNDRIES INC.
- Suraj K. PATIL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INLINE BURIED METAL VOID DETECTION BY SURFACE PLASMON RESONANCE (SPR)
- Publication number 20170016822
- Publication date Jan 19, 2017
- GLOBALFOUNDRIES INC.
- Sabarinath JAYASEELAN
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS...
- Publication number 20160351675
- Publication date Dec 1, 2016
- GLOBALFOUNDRIES, Inc.
- Suraj K. Patil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FABRICATION METHODS FOR MULTI-LAYER SEMICONDUCTOR STRUCTURES
- Publication number 20160190014
- Publication date Jun 30, 2016
- GLOBALFOUNDRIES INC.
- Suraj K. PATIL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE LAYER INTERFACE FORMATION FOR SEMICONDUCTOR STRUCTURE
- Publication number 20160118468
- Publication date Apr 28, 2016
- GLOBALFOUNDRIES INC.
- Suraj K. PATIL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MASK STRUCTURES AND METHODS OF MANUFACTURING
- Publication number 20150212402
- Publication date Jul 30, 2015
- GLOBALFOUNDRIES INC.
- Suraj K. PATIL
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
FACILITATING ETCH PROCESSING OF A THIN FILM VIA PARTIAL IMPLANTATIO...
- Publication number 20150104948
- Publication date Apr 16, 2015
- GLOBALFOUNDRIES INC.
- Suraj K. PATIL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and Apparatus for Fabricating Piezoresistive Polysilicon by...
- Publication number 20140091410
- Publication date Apr 3, 2014
- Board of Regents, The University of Texas System
- Zeynep Celik-Butler
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR FABRICATING PIEZORESISTIVE POLYSILICON BY...
- Publication number 20100102403
- Publication date Apr 29, 2010
- Board of Regents, The University of Texas System
- Zeynep Celik-Butler
- G01 - MEASURING TESTING

Suraj Kumar Patil

Person

Patents Grantslast 30 patents

Integration scheme for gate height control and void free RMG fill

Heterogeneous integration of 3D SI and III-V vertical nanowire stru...

Integration of gate structures and spacers with air gaps

Integration scheme for gate height control and void free RMG fill

Programmable via devices with metal/semiconductor via links and fab...

Structure and method for capping cobalt contacts

Methods of forming MIS contact structures on transistor devices

Method, apparatus, and system for E-fuse in advanced CMOS technologies

Programmable via devices with metal/semiconductor via links and fab...

Heterogeneous integration of 3D Si and III-V vertical nanowire stru...

Semiconductor structure with anti-efuse device

Integrated circuits with replacement metal gates and methods for fa...

Programmable devices with current-facilitated migration and fabrica...

Method, apparatus, and system for e-fuse in advanced CMOS technologies

Facilitating etch processing of a thin film via partial implantatio...

Methods of forming MIS contact structures on transistor devices in...

Inline buried metal void detection by surface plasmon resonance (SPR)

Multiple layer interface formation for semiconductor structure

Methods for fabricating programmable devices and related structures

Fabrication methods for multi-layer semiconductor structures

MOL contact metallization scheme for improved yield and device reli...

Mask structures and methods of manufacturing

Method and apparatus for fabricating piezoresistive polysilicon by...

Method and apparatus for fabricating piezoresistive polysilicon by...

Patents Applicationslast 30 patents

METHODS FOR FORMING IC STRUCTURE HAVING RECESSED GATE SPACERS AND R...

GATE STACK PROCESSES AND STRUCTURES

INTEGRATION SCHEME FOR GATE HEIGHT CONTROL AND VOID FREE RMG FILL

STRUCTURE AND METHOD FOR CAPPING COBALT CONTACTS

ENCAPSULATION OF COBALT METALLIZATION

STRUCTURE AND METHOD FOR CAPPING COBALT CONTACTS

PROGRAMMABLE VIA DEVICES WITH METAL/SEMICONDUCTOR VIA LINKS AND FAB...

INTERCONNECTS WITH INNER SACRIFICIAL SPACERS

HETEROGENEOUS INTEGRATION OF 3D SI AND III-V VERTICAL NANOWIRE STRU...

METHODS OF FORMING MIS CONTACT STRUCTURES ON TRANSISTOR DEVICES

METHOD, APPARATUS, AND SYSTEM FOR E-FUSE IN ADVANCED CMOS TECHNOLOGIES

ON-CHIP VARIABLE CAPACITOR WITH GEOMETRIC CROSS-SECTION

METHOD, APPARATUS, AND SYSTEM FOR E-FUSE IN ADVANCED CMOS TECHNOLOGIES

SEMICONDUCTOR STRUCTURE WITH ANTI-EFUSE DEVICE

PROGRAMMABLE DEVICES WITH CURRENT-FACILITATED MIGRATION AND FABRICA...

PROGRAMMABLE VIA DEVICES WITH METAL/SEMICONDUCTOR VIA LINKS AND FAB...

METHODS FOR FABRICATING PROGRAMMABLE DEVICES AND RELATED STRUCTURES

INLINE BURIED METAL VOID DETECTION BY SURFACE PLASMON RESONANCE (SPR)

INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS...

FABRICATION METHODS FOR MULTI-LAYER SEMICONDUCTOR STRUCTURES

MULTIPLE LAYER INTERFACE FORMATION FOR SEMICONDUCTOR STRUCTURE

MASK STRUCTURES AND METHODS OF MANUFACTURING

FACILITATING ETCH PROCESSING OF A THIN FILM VIA PARTIAL IMPLANTATIO...

Method and Apparatus for Fabricating Piezoresistive Polysilicon by...

METHOD AND APPARATUS FOR FABRICATING PIEZORESISTIVE POLYSILICON BY...