Patent Application
20190096679
The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures for a field-effect transistor and methods of forming a field-effect transistor.
Device structures for a field-effect transistor generally include a body region, a source and a drain defined in the body region, and a gate electrode configured to switch carrier flow in a channel formed during device operation in the body region. When a control voltage exceeding a designated threshold voltage is applied to the gate electrode, carrier flow occurs in an inversion or depletion layer in the channel between the source and drain to produce a device output current.
The gate electrode may include one or more work function metal layers and a fill layer composed of tungsten. The conventional process for forming the fill layer utilizes chemical vapor deposition and tungsten hexafluoride (WF6) as a tungsten precursor source. The use of tungsten hexafluoride has associated deficiencies, such as corrosion of work function metals deriving from fluorine produced as a byproduct gas during tungsten chemical vapor deposition. Corrosion may be mitigated by covering the work function metal with a layer of a barrier metal that blocks the passage of fluorine during the formation of the tungsten fill layer. However, the barrier metal layer occupies a significant amount of space inside the gate cavity, which may elevate the electrical resistance of the gate electrode because the barrier metal may have a higher electrical resistivity than tungsten.
In embodiments of the invention, a method is provided for forming a field-effect transistor. The method includes forming a gate cavity in a dielectric layer that includes a bottom surface and a plurality of sidewalls extending to the bottom surface, and forming a gate dielectric layer at the sidewalls and the bottom surface of the gate cavity. A work function metal layer is deposited on the gate dielectric layer at the sidewalls and the bottom surface of the gate cavity. After the work function metal layer is deposited, a fill metal layer is deposited inside the gate cavity. The fill metal layer is formed in direct contact with the work function metal layer.
In embodiments of the invention, a structure is provided for a field-effect transistor. The structure includes a dielectric layer with a gate cavity having a bottom surface and a plurality of sidewalls that extend to the bottom surface. The structure further includes a gate dielectric layer at the sidewalls and the bottom surface of the gate cavity, a work function metal layer on the gate dielectric layer at the sidewalls and the bottom surface of the gate cavity, and a fill metal layer inside the gate cavity. The fill metal layer has a directly contacting relationship with the work function metal layer.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention.
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The gate cavity 12 may penetrate through the thickness of the one or more dielectric layers 10 to a top surface of a substrate 18, such as the top surface of a semiconductor fin. The gate cavity 12 may be formed by the removal of a sacrificial gate structure from the space between the dielectric spacers 17. The term “sacrificial gate structure” as used herein refers to a placeholder structure for a functional gate structure to be subsequently formed. The term “functional gate structure” as used herein refers to a permanent gate structure used to control output current (i.e., flow of carriers in the channel) of a field-effect transistor.
The gate dielectric layer 14 includes vertical sections arranged between the conductor layer 16 and the sidewalls 11 of the gate cavity 12 and a horizontal section arranged between the conductor layer 16 and the bottom surface 13 of the gate cavity 12. The gate dielectric layer 14 may be composed of a dielectric material, such as a high-k dielectric having a dielectric constant (i.e., permittivity) greater than the dielectric constant of silicon dioxide (SiO2). High-k dielectric materials suitable for the gate dielectric layer 14 include, but are not limited to, a hafnium-based dielectric material like hafnium oxide (HfO2), a layered stack of a hafnium-based dielectric material and another dielectric material (e.g., aluminum oxide (Al2O3)), or combinations of these and other dielectric materials, deposited by atomic layer deposition (ALD).
The conductor layer 16 may be composed of a work function metal deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD). The composition of the conductor layer 16 may be selected for forming a gate electrode of either an n-type field-effect transistor or a p-type field-effect transistor. In an embodiment, the work function metal of conductor layer 16 may be composed of titanium nitride (TiN) used in a gate stack forming a gate electrode of a p-type field-effect transistor, and may be patterned to remove the conductor layer from gate cavities (not shown) in regions used to fabricate n-type field-effect transistors.
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A conductor layer 24 is formed that conformally covers the conductor layer 22 inside the gate cavity 12. The conductor layer 24 is composed of fluorine-free tungsten (W) formed by ALD using a tungsten-containing precursor source that does not contain fluorine as a component. The conductor layer 24 is formed in the same deposition tool as conductor layers 20, 22 such that an air break is not present between the successive depositions. The conductor layer 24 is formed in the metal gate stack as a replacement for a conventional barrier metal layer.
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The space opened in the gate cavity 12 may be filled by a dielectric cap 29 composed of, for example, silicon nitride (Si3N4) deposited by CVD and planarized with CMP. The dielectric cap 29 may be subsequently used in a self-aligned contact process that is performed during MOL processing to contact the functional gate structure 28. The dielectric cap 29 has an exposed top surface and a bottom surface that is in direct contact with the conductor layers 20, 22, 24, 26.
Middle-of-line (MOL) and back-end-of-line (BEOL) processing follow, which includes formation of contacts and wiring for the local interconnect structure overlying the device structure, and formation of dielectric layers, via plugs, and wiring for an interconnect structure coupled by the interconnect wiring with the functional gate structure 28 and other elements (e.g., source/drain regions) of the field-effect transistor 30.
The embodiments of the invention may mitigate the formation of keyholes or voids during the final recess before the formation of the dielectric cap 29 because a conductor layer 26 comprised of tungsten formed by CVD is the primary material that is recessed. The result is an improved yield in comparison with only recessing work function metals in the final recess, as is conventional. The embodiments of the invention may increase the space available in the gate cavity 12 for low-resistivity tungsten, which may result in improved device performance. The increased space is the result, at least in part, of inserting a chamfer after the conductor layer 16 before the conductor layers 20, 22 are formed, and replacing the conventional barrier metal layer (e.g., TiN) with the conductor layer 24 that is composed of a lower resistivity material, e.g., fluorine-free tungsten.
An n-type field-effect transistor 30 may exhibit a reduced threshold voltage because the gate stack including the conductor layers 20, 22 can be kept thin by replacing the capping barrier metal layer with the conductor layer 24 composed of fluorine-free tungsten. The conductor layer 24 composed of fluorine-free tungsten may be effective to prevent fluorine from attacking one or more of the conductor layers 20, 22 (e.g., Al-containing titanium aluminum carbide (TiA1C) in conductor layer 22). In addition, the ability to omit the chamfer of the conductor layers 20, 22 avoids the need to remove an associated etch mask, which could otherwise introduce oxygen originating from an oxygen plasma as an impurity into conductor layer 20 and/or conductor layer 22.
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The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (e.g., a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product.
References herein to terms such as “vertical”, “horizontal”, “lateral”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. Terms such as “horizontal” and “lateral” refer to a direction in a plane parallel to a top surface of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. Terms such as “vertical” and “normal” refer to a direction perpendicular to the “horizontal” and “lateral” direction. Terms such as “above” and “below” indicate positioning of elements or structures relative to each other and/or to the top surface of the semiconductor substrate as opposed to relative elevation.
A feature “connected” or “coupled” to or with another element may be directly connected or coupled to the other element or, instead, one or more intervening elements may be present. A feature may be “directly connected” or “directly coupled” to another element if intervening elements are absent. A feature may be “indirectly connected” or “indirectly coupled” to another element if at least one intervening element is present.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
