Patent Application
20180012791
The present invention relates to integrated circuits and semiconductor device fabrication and, more specifically, to interconnect structures for a chip and methods of forming such interconnect structures.
A back-end-of-line (BEOL) interconnect structure may be used to electrically connect device structures fabricated on a substrate by front-end-of-line (FEOL) processing. The BEOL interconnect structure may be formed using a dual damascene process in which via openings and trenches etching in a dielectric layer are simultaneously filled with metal to create a metallization level. In a via-first, trench-last dual damascene processing process in which a via opening is formed in a dielectric layer and then a trench is formed above the via opening, the via openings are unfilled during the etching process forming the trenches. In a single damascene process, the via openings and trenches are formed in different dielectric layers and filled separately with metal.
Improved interconnect structures for a chip and methods of forming such interconnect structures are needed.
According to an embodiment of the invention, an interconnect structure includes a dielectric layer including an opening, a conductive plug inside the opening in the dielectric layer, and an air gap inside the opening in the dielectric layer at a location between the conductive plug and the opening in the dielectric layer.
According to another embodiment of the invention, a method includes forming an opening in a dielectric layer, and forming a spacer inside the opening in the dielectric layer. After the spacer is formed, a conductive plug is formed inside the opening in the dielectric layer. After the conductive plug is formed, the spacer is removed to form an air gap inside the opening in the dielectric layer. The air gap is located between the conductive plug and the opening in the dielectric layer.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention.
With reference to
Openings, of which openings 14, 16 are representative, may be formed by photolithography and etching at selected locations distributed across the surface area of dielectric layer 12. Specifically, a resist layer may be applied, exposed to a pattern of radiation projected through a photomask, and developed to form a corresponding pattern of openings situated at the intended locations for the openings 14, 16 to be formed in the dielectric layer 12. The patterned resist layer is used as an etch mask for a dry etching process, such as a reactive-ion etching (REI), that removes portions of the dielectric layer 12 to form the openings 14, 16. The etching process may be conducted in a single etching step or multiple etching steps with different etch chemistries, and may open onto an underlying feature (not shown). The feature may be a conductive feature in an underlying dielectric layer that is aligned with the openings 14, 16. The opening 14 has sidewalls 14a, which may be vertical, that terminate at, and are connected by, a base surface 14b. Similarly, the opening 16 has sidewalls 16a, which may also be vertical, that terminate at, and are connected by, a base surface 16b proximate to the substrate 13.
A conformal layer 15 comprised of a given material that is chosen to selectively etch relative to the dielectric layer 12 is deposited that covers the sidewalls 14a, 16a and base surfaces 14b, 16b of the openings 14, 16. The conformal layer 15 has a layer thickness that is selected in conjunction with dimensions (e.g., a width dimension) of the openings 14, 16 in order to establish one or more dimensions for air gaps that are subsequently formed as described supra. The conformal layer 15 may also form in the field area on the top surface of the dielectric layer 12. The thickness of the conformal layer 15 is nominally the same at any location on the sidewalls 14a, 16a, base surfaces 14b, 16b, and the top surface of the dielectric layer 12 in the field area.
With reference to
As mentioned infra, the material constituting the conformal layer 15 and, thus, the sacrificial spacers 18, 20 is selected to etch selectively to (i.e., at a higher etch rate than) the material of the dielectric layer 12 for ease of removal. In an embodiment, the conformal layer 15 and sacrificial spacers 18 may be constituted by a dielectric material formed from a layer of the dielectric material deposited by, for example, CVD. If the constituent dielectric material is specifically silicon nitride (Si3N4), the selective removal may be accomplished using, for example, hot phosphoric acid (H2SO4). If the constituent dielectric material is specifically silicon dioxide (SiO2), the selective removal may be accomplished using, for example, diluted hydrofluoric acid (HF). If the constituent dielectric material is specifically phosphorus silicon glass (PSG), the selective removal may be accomplished using, for example, diluted hydrofluoric acid (HF).
In other embodiments, the conformal layer 15 and sacrificial spacers 18, 20 may be comprised of other types of materials, such as titanium nitride that can be selectively removed using, for example, a post etch residue remover (e.g., EKC) or amorphous silicon that can be selectively removed using, for example, tetramethylammonium hydroxide (TMAH).
With reference to
After the deposition of the seed layer, a thicker conductor or metal layer 24 comprised of a low-resistivity metal, such as copper (Cu), may be deposited using a deposition process, such as electroplating or another electrochemical plating process, different than the deposition process used to deposit the seed layer. The seed layer may be required to carry the electrical current needed to initiate an electroplating process forming the metal layer 24 and may be subsumed into the metal layer 24. Respective residual portions of the seed layer and metal layer 24 are located inside the openings 14, 16. Alternatively, the metal layer 24 may be deposited with an electroless deposition process, which would permit the seed layer to be omitted.
With reference to
A metal cap 30 is formed on the top surface of each metal plugs 26, 28 by selective deposition with, for example, CVD, which in this instance entails inducing a chemical reaction between a metal precursor and a co-reactant gas in the vicinity of the top surfaces of the metal plugs 26, 28. A solid reaction product is selectively deposited to form the metal plugs 26, 28. However, the reaction product does not form on the top surface of the dielectric layer 12 adjacent to the metal caps 30. The deposition conditions may be selected to provide a thin film that is highly conductive (i.e., low electrical resistance) and that exhibits good adhesion to cobalt without depositing on dielectric surfaces. In particular, the conductor in the metal caps 30 may be composed of ruthenium (Ru), a ruthenium-containing material (e.g., ruthenium oxide (RuOx)), cobalt (Co), or a cobalt-containing material (e.g., cobalt tungsten phosphide (CoWP)), deposited by low-temperature CVD. The metal caps 30 function to protect the top surfaces of the metal plugs 26, 28 during subsequent cleaning and etching processes against erosion or damage.
With reference to
The spaces vacated by the removed sacrificial spacers 18, 20 define air gaps 36, 38 that are unfilled by solid material. The air gaps 36, 38, which replace the sacrificial spacers 18, 20, may have one or more dimensions that are nominally equal to the dimensions of the sacrificial spacers 18, 20 following the polishing process that removes the metal layer 24 from the field area on the top surface of the dielectric layer 12. In an embodiment, the width of the air gaps 36, 38 is equal to the layer thickness of the sacrificial spacers 18, 20. The air gap 36 is located between the sidewall 14a of the opening 14 and the nearest exterior sidewall 26a of the metal plug 26 across the spatial gap created by the air gap 36. Similarly, the air gap 38 is located between the sidewall 16a of the opening 16 and the nearest exterior sidewall 28a of the metal plug 28 across the spatial gap created by the air gap 38. The metal plugs 26, 28 are located between the different sections of the respective associated air gaps 32, 38. The air gap 36 extends vertically from one end at the base surface 14b to an open end at the top surface of the dielectric layer 12. Similarly, the air gap 38 extends vertically from one end at the base surface 16b to an open end at the top surface of the dielectric layer 12. The air gap 36 and the metal plug 26 are coextensive with the base surface 14b of the opening 14 in the dielectric layer 12, and the metal plug 26 is coplanar with a portion of the perimeter of the air gap 36 at the base surface 14b. The air gap 38 and the metal plug 28 are coextensive with the base surface 16b of the opening 16 in the dielectric layer 12, and the metal plug 28 is coplanar with a portion of the perimeter of the air gap 38 at the base surface 16b.
The metal plug 26 is located between different sections of the associated air gap 32. Similarly, the metal plug 28 is located between the different sections of the associated air gap 38. In an embodiment, the air gaps 36, 38 may each extend about the perimeter of the associated one of the metal plugs 26, 28 such that the air gaps 36, 38 represent continuous open spaces that surround the respective metal plugs 26, 28.
The air gaps 36, 38 may have a dielectric constant (e.g., relative permittivity) of near unity (i.e., about 1.0), which reflects that the air gaps 36, 38 are filled by air at or near atmospheric pressure, are filled by another gas at or near atmospheric pressure, or contain air or gas at a sub-atmospheric pressure (e.g., a partial vacuum). The dielectric constant is given by the ratio of the permittivity of a substance to the permittivity of a vacuum. Because the air gaps 36, 38 have a dielectric constant that is less than the dielectric constant of the material constituting the dielectric layer 12, the composite dielectric constant of the dielectric material proximate to each of the metal plugs 26, 28 is reduced.
A liner (not shown) may be formed that covers the dielectric material of dielectric layer 12 and the metal plugs 26, 28 that border the air gaps 36, 38. The liner may be comprised of an electrical insulator with a dielectric constant characteristic of a dielectric material, such as a high temperature oxide (HTO) deposited using a rapid thermal process (RTP).
With reference to
Because the sacrificial spacers 18, 20 narrow the openings 14, 16, a larger process margin exists for the lithography process used to form the openings 14, 16. In other words, the openings 14, 16 may be formed in the dielectric layer 12 with larger dimensions and subsequently narrowed with the formation of the sacrificial spacers 18, 20 before the metal plugs 26, 28 are formed. The dimensions of the metal plugs 26, 28 are less than the dimensions of the openings 14, 16 because of the presence of the sacrificial spacers 18, 20. The air gaps 36, 38, which have a relative permittivity that is less than the relative permittivity of the dielectric layer 12, operate to reduce the capacitance of the metallization level 10. The profile of the openings 14, 16 with the inner sacrificial spacers 18 may be friendly to deposition of the barrier/liner layer 22 and the plating used to form the metal layer 24, which may reduce the incidence of metal (e.g., copper) voiding in the metal plugs 26, 28. The volume of the air gaps 36, 38 is predictable and controllable at least in part through control over the dimensions of the sacrificial spacers 18.
The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. The chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product. The end product can be any product that includes integrated circuit chips, such as computer products having a central processor or smartphones.
References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refers to a direction perpendicular to the horizontal, as just defined. The term “lateral” refers to a direction within the horizontal plane. Terms such as “above” and “below” are used to indicate positioning of elements or structures relative to each other as opposed to relative elevation.
A feature may be “connected” or “coupled” to or with another element may be directly connected or coupled to the other element or, instead, one or more intervening elements may be present. A feature may be “directly connected” or “directly coupled” to another element if intervening elements are absent. A feature may be “indirectly connected” or “indirectly coupled” to another element if at least one intervening element is present.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
