Terence G. Blake

Person

Dallas, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Array-based integrated circuit with reduced proximity effects
- Patent number 8,472,229
- Issue date Jun 25, 2013
- Texas Instruments Incorporated
- Xiaowei Deng
- G11 - INFORMATION STORAGE
Information Patent Grant
Array-based integrated circuit with reduced proximity effects
- Patent number 8,472,228
- Issue date Jun 25, 2013
- Texas Instruments Incorporated
- Xiaowei Deng
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile SRAM
- Patent number 6,980,459
- Issue date Dec 27, 2005
- Texas Instruments Incorporated
- Anand Seshadri
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage level shifter with testable cascode devices
- Patent number 6,487,687
- Issue date Nov 26, 2002
- Texas Instruments Incorporated
- Terence G. W. Blake
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Output buffer with switching PMOS drivers
- Patent number 6,157,223
- Issue date Dec 5, 2000
- Texas Instruments Incorporated
- Terence G. W. Blake
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Output buffer having quasi-failsafe operation
- Patent number 6,040,708
- Issue date Mar 21, 2000
- Texas Instruments Incorporated
- Terence G. W. Blake
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Output buffer providing testability
- Patent number 5,995,010
- Issue date Nov 30, 1999
- Texas Instruments Incorporated
- Terence G. W. Blake
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory cell with capacitance for single event upset protection
- Patent number 5,917,212
- Issue date Jun 29, 1999
- Texas Instruments Incorporated
- Terence G. W. Blake
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell with capacitance for single event upset protection
- Patent number 5,204,990
- Issue date Apr 20, 1993
- Texas Instruments Incorporated
- Terence G. W. Blake
- G11 - INFORMATION STORAGE
Information Patent Grant
On-chip transient event detector
- Patent number 5,107,139
- Issue date Apr 21, 1992
- Texas Instruments Incorporated
- Theodore W. Houston
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
SOI layout for low resistance gate
- Patent number 5,079,604
- Issue date Jan 7, 1992
- Texas Instruments Incorporated
- Theodore W. Houston
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon-on-insulator transistor with selectable body node to source...
- Patent number 5,079,605
- Issue date Jan 7, 1992
- Texas Instruments Incorporated
- Terence G. W. Blake
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SEU hardened memory cell
- Patent number 5,046,044
- Issue date Sep 3, 1991
- Texas Instruments Incorporated
- Theodore W. Houston
- G11 - INFORMATION STORAGE
Information Patent Grant
MOS transistor with improved radiation hardness
- Patent number 5,026,656
- Issue date Jun 25, 1991
- Texas Instruments Incorporated
- Mishel Matloubian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
MOS transistor with improved radiation hardness
- Patent number 4,974,051
- Issue date Nov 27, 1990
- Texas Instruments Incorporated
- Mishel Matloubian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon-on-insulator transistor with body node to source node conne...
- Patent number 4,965,213
- Issue date Oct 23, 1990
- Texas Instruments Incorporated
- Terence G. W. Blake
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for making high performance silicon-on-insulator transistor...
- Patent number 4,946,799
- Issue date Aug 7, 1990
- Texas Instruments, Incorporated
- Terence G. W. Blake
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cell including single event upset rate reduction circuitry
- Patent number 4,914,629
- Issue date Apr 3, 1990
- Texas Instruments, Incorporated
- Terence G. W. Blake
- G11 - INFORMATION STORAGE
Information Patent Grant
Single event upset hardened memory cell
- Patent number 4,912,675
- Issue date Mar 27, 1990
- Texas Instruments, Incorporated
- Terence G. W. Blake
- G11 - INFORMATION STORAGE
Information Patent Grant
Making a silicon-on-insulator transistor with selectable body node...
- Patent number 4,906,587
- Issue date Mar 6, 1990
- Texas Instruments Incorporated
- Terence G. W. Blake
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High performance silicon-on-insulator transistor with body node to...
- Patent number 4,899,202
- Issue date Feb 6, 1990
- Texas Instruments Incorporated
- Terence G. W. Blake
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory with p-channel cell access transistors
- Patent number 4,623,989
- Issue date Nov 18, 1986
- Texas Instruments Incorporated
- Terence G. Blake
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
ARRAY-BASED INTEGRATED CIRCUIT WITH REDUCED PROXIMITY EFFECTS
- Publication number 20130044536
- Publication date Feb 21, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Xiaowei Deng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Array-Based Integrated Circuit with Reduced Proximity Effects
- Publication number 20120106225
- Publication date May 3, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Xiaowei Deng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Non-volatile SRAM
- Publication number 20040080972
- Publication date Apr 29, 2004
- Anand Seshadri
- G11 - INFORMATION STORAGE

Terence G. Blake

Person

Patents Grantslast 30 patents

Array-based integrated circuit with reduced proximity effects

Array-based integrated circuit with reduced proximity effects

Non-volatile SRAM

Voltage level shifter with testable cascode devices

Output buffer with switching PMOS drivers

Output buffer having quasi-failsafe operation

Output buffer providing testability

Memory cell with capacitance for single event upset protection

Memory cell with capacitance for single event upset protection

On-chip transient event detector

SOI layout for low resistance gate

Silicon-on-insulator transistor with selectable body node to source...

SEU hardened memory cell

MOS transistor with improved radiation hardness

MOS transistor with improved radiation hardness

Silicon-on-insulator transistor with body node to source node conne...

Process for making high performance silicon-on-insulator transistor...

Memory cell including single event upset rate reduction circuitry

Single event upset hardened memory cell

Making a silicon-on-insulator transistor with selectable body node...

High performance silicon-on-insulator transistor with body node to...

Memory with p-channel cell access transistors

Patents Applicationslast 30 patents

ARRAY-BASED INTEGRATED CIRCUIT WITH REDUCED PROXIMITY EFFECTS

Array-Based Integrated Circuit with Reduced Proximity Effects

Non-volatile SRAM