Thomas Scott Morris

Person

Lewisville, NC, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of fabricating contact pads for electronic substrates
- Patent number 11,765,826
- Issue date Sep 19, 2023
- Qorvo US, Inc.
- John August Orlowski
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Shielded electronic modules and methods of forming the same utilizi...
- Patent number 11,387,190
- Issue date Jul 12, 2022
- Qorvo US, Inc.
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electromagnetic shields for sub-modules
- Patent number 11,219,144
- Issue date Jan 4, 2022
- Qorvo US, Inc.
- Kelly M. Lear
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Segmented shielding using wirebonds
- Patent number 11,127,689
- Issue date Sep 21, 2021
- Qorvo US, Inc.
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electromagnetic shields for sub-modules
- Patent number 11,058,038
- Issue date Jul 6, 2021
- Qorvo US, Inc.
- Kelly M. Lear
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Process for molding a back side wafer singulation guide
- Patent number 11,024,541
- Issue date Jun 1, 2021
- Qorvo US, Inc.
- Neftali Salazar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Contact pads for electronic substrates and related methods
- Patent number 10,905,007
- Issue date Jan 26, 2021
- Qorvo US, Inc.
- John August Orlowski
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Double-sided module with electromagnetic shielding
- Patent number 10,888,040
- Issue date Jan 5, 2021
- Qorvo US, Inc.
- David Jandzinski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Double-sided module with electromagnetic shielding
- Patent number 10,856,456
- Issue date Dec 1, 2020
- Qorvo US, Inc.
- David Jandzinski
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Shielded electronic modules and methods of forming the same utilizi...
- Patent number 10,811,364
- Issue date Oct 20, 2020
- Qorvo US, Inc.
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Using an interconnect bump to traverse through a passivation layer...
- Patent number 10,777,524
- Issue date Sep 15, 2020
- Qorvo US, Inc.
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate structure with selective surface finishes for flip chip a...
- Patent number 10,607,960
- Issue date Mar 31, 2020
- Qorvo US, Inc.
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electromagnetic shielding for integrated circuit modules
- Patent number 10,553,545
- Issue date Feb 4, 2020
- Qorvo US, Inc.
- Donald Joseph Leahy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate structure with selective surface finishes for flip chip a...
- Patent number 10,283,480
- Issue date May 7, 2019
- Qorvo US, Inc.
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Encapsulated dies with enhanced thermal performance
- Patent number 10,020,206
- Issue date Jul 10, 2018
- Qorvo US, Inc.
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Encapsulated dies with enhanced thermal performance
- Patent number 9,997,376
- Issue date Jun 12, 2018
- Qorvo US, Inc.
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Encapsulated dies with enhanced thermal performance
- Patent number 9,960,054
- Issue date May 1, 2018
- Qorvo US, Inc.
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flip chip module with enhanced properties
- Patent number 9,960,145
- Issue date May 1, 2018
- Qorvo US, Inc.
- Julio C. Costa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Connection using conductive vias
- Patent number 9,942,994
- Issue date Apr 10, 2018
- Qorvo US, Inc.
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package having a substrate structure with selective s...
- Patent number 9,935,066
- Issue date Apr 3, 2018
- Qorvo US, Inc.
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flip chip module with enhanced properties
- Patent number 9,929,125
- Issue date Mar 27, 2018
- Qorvo US, Inc.
- Julio C. Costa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Encapsulated dies with enhanced thermal performance
- Patent number 9,929,024
- Issue date Mar 27, 2018
- Qorvo US, Inc.
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Laminate variables measured electrically
- Patent number 9,897,512
- Issue date Feb 20, 2018
- Qorvo US, Inc.
- Thomas Scott Morris
- B06 - GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
Information Patent Grant
Flip chip module with enhanced properties
- Patent number 9,899,350
- Issue date Feb 20, 2018
- Qorvo US, Inc.
- Julio C. Costa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Encapsulated dies with enhanced thermal performance
- Patent number 9,892,937
- Issue date Feb 13, 2018
- Qorvo US, Inc.
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Encapsulated dies with enhanced thermal performance
- Patent number 9,859,132
- Issue date Jan 2, 2018
- Qorvo US, Inc.
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic modules having grounded electromagnetic shields
- Patent number 9,661,739
- Issue date May 23, 2017
- Qorvo US, Inc.
- Donald Joseph Leahy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low pressure encapsulant for size-reduced semiconductor package
- Patent number 9,646,857
- Issue date May 9, 2017
- Qorvo US, Inc.
- Howard Terry Glascock
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Encapsulated dies with enhanced thermal performance
- Patent number 9,613,831
- Issue date Apr 4, 2017
- Qorvo US, Inc.
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Encapsulated dies with enhanced thermal performance
- Patent number 9,576,822
- Issue date Feb 21, 2017
- Qorvo US, Inc.
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR DIE LEVEL STRESS DETECTION IN PACKAGE UTILIZING STRAI...
- Publication number 20240426682
- Publication date Dec 26, 2024
- Qorvo US, Inc.
- Thomas Scott Morris
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM IN A PACKAGE (SIP) WITH AIR CAVITY AND EPOXY SEAL
- Publication number 20230402333
- Publication date Dec 14, 2023
- Qorvo US, Inc.
- MD Hasnine
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMPARTMENTALIZED SHIELDING OF A MODULE UTILIZING SELF-SHIELDED SUB...
- Publication number 20230247814
- Publication date Aug 3, 2023
- Qorvo US, Inc.
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC DEVICE WITH SOLDER INTERCONNECT AND MULTIPLE MATERIAL EN...
- Publication number 20220052667
- Publication date Feb 17, 2022
- Qorvo US, Inc.
- Charles E. Carpenter
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CONTACT PADS FOR ELECTRONIC SUBSTRATES AND RELATED METHODS
- Publication number 20210144853
- Publication date May 13, 2021
- Qorvo US, Inc.
- John August Orlowski
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SHIELDED ELECTRONIC MODULES AND METHODS OF FORMING THE SAME UTILIZI...
- Publication number 20210020583
- Publication date Jan 21, 2021
- Qorvo US, Inc.
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACT PADS FOR ELECTRONIC SUBSTRATES AND RELATED METHODS
- Publication number 20210007224
- Publication date Jan 7, 2021
- Qorvo US, Inc.
- John August Orlowski
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SHIELDED ELECTRONIC MODULES AND METHODS OF FORMING THE SAME UTILIZI...
- Publication number 20200303318
- Publication date Sep 24, 2020
- Qorvo US, Inc.
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTROMAGNETIC SHIELDS FOR SUB-MODULES
- Publication number 20200305314
- Publication date Sep 24, 2020
- Qorvo US, Inc.
- Kelly M. Lear
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FOR MOLDING A BACK SIDE WAFER SINGULATION GUIDE
- Publication number 20200111708
- Publication date Apr 9, 2020
- Qorvo US, Inc.
- Neftali Salazar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTROMAGNETIC SHIELDS FOR SUB-MODULES
- Publication number 20200008327
- Publication date Jan 2, 2020
- Qorvo US, Inc.
- Kelly M. Lear
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SEGMENTED SHIELDING USING WIREBONDS
- Publication number 20190371738
- Publication date Dec 5, 2019
- Qorvo US, Inc.
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE STRUCTURE WITH SELECTIVE SURFACE FINISHES FOR FLIP CHIP A...
- Publication number 20190229087
- Publication date Jul 25, 2019
- Qorvo US, Inc.
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DOUBLE-SIDED MODULE WITH ELECTROMAGNETIC SHIELDING
- Publication number 20190104653
- Publication date Apr 4, 2019
- Qorvo US, Inc.
- David Jandzinski
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
USING AN INTERCONNECT BUMP TO TRAVERSE THROUGH A PASSIVATION LAYER...
- Publication number 20180366431
- Publication date Dec 20, 2018
- Qorvo US, Inc.
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTROMAGNETIC SHIELDING FOR INTEGRATED CIRCUIT MODULES
- Publication number 20180204804
- Publication date Jul 19, 2018
- Qorvo US, Inc.
- Donald Joseph Leahy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW PRESSURE ENCAPSULANT FOR SIZE-REDUCED SEMICONDUCTOR PACKAGE
- Publication number 20170047232
- Publication date Feb 16, 2017
- Qorvo US, Inc.
- Howard Terry Glascock
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE STRUCTURE WITH SELECTIVE SURFACE FINISHES FOR FLIP CHIP A...
- Publication number 20170040276
- Publication date Feb 9, 2017
- Qorvo US, Inc.
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE HAVING A SUBSTRATE STRUCTURE WITH SELECTIVE S...
- Publication number 20170040273
- Publication date Feb 9, 2017
- Qorvo US, Inc.
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
USING AN INTERCONNECT BUMP TO TRAVERSE THROUGH A PASSIVATION LAYER...
- Publication number 20170018520
- Publication date Jan 19, 2017
- Qorvo US, Inc.
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLIP CHIP MODULE WITH ENHANCED PROPERTIES
- Publication number 20160343592
- Publication date Nov 24, 2016
- Qorvo US, Inc.
- Julio C. Costa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENCAPSULATED DIES WITH ENHANCED THERMAL PERFORMANCE
- Publication number 20160284568
- Publication date Sep 29, 2016
- RF Micro Devices, Inc.
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENCAPSULATED DIES WITH ENHANCED THERMAL PERFORMANCE
- Publication number 20160284570
- Publication date Sep 29, 2016
- RF Micro Devices, Inc.
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONNECTION USING CONDUCTIVE VIAS
- Publication number 20150296631
- Publication date Oct 15, 2015
- RF Micro Devices, Inc.
- Thomas Scott Morris
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
ELECTRONIC MODULES HAVING GROUNDED ELECTROMAGNETIC SHIELDS
- Publication number 20150124421
- Publication date May 7, 2015
- RF Micro Devices, Inc.
- Donald Joseph Leahy
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
CONNECTION USING CONDUCTIVE VIAS
- Publication number 20140340859
- Publication date Nov 20, 2014
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SURFACE FINISH FOR CONDUCTIVE FEATURES ON SUBSTRATES
- Publication number 20140146489
- Publication date May 29, 2014
- John August Orlowski
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
USING AN INTERCONNECT BUMP TO TRAVERSE THROUGH A PASSIVATION LAYER...
- Publication number 20140021603
- Publication date Jan 23, 2014
- RF Micro Devices, Inc.
- Thomas Scott Morris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAMINATE VARIABLES MEASURED ELECTRICALLY
- Publication number 20120262189
- Publication date Oct 18, 2012
- RF Micro Devices, Inc.
- Thomas Scott Morris
- G01 - MEASURING TESTING
Information Patent Application
CONNECTION USING CONDUCTIVE VIAS
- Publication number 20120217624
- Publication date Aug 30, 2012
- RF Micro Devices, Inc.
- Thomas Scott Morris
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Thomas Scott Morris

Person

Patents Grantslast 30 patents

Method of fabricating contact pads for electronic substrates

Shielded electronic modules and methods of forming the same utilizi...

Electromagnetic shields for sub-modules

Segmented shielding using wirebonds

Electromagnetic shields for sub-modules

Process for molding a back side wafer singulation guide

Contact pads for electronic substrates and related methods

Double-sided module with electromagnetic shielding

Double-sided module with electromagnetic shielding

Shielded electronic modules and methods of forming the same utilizi...

Using an interconnect bump to traverse through a passivation layer...

Substrate structure with selective surface finishes for flip chip a...

Electromagnetic shielding for integrated circuit modules

Substrate structure with selective surface finishes for flip chip a...

Encapsulated dies with enhanced thermal performance

Encapsulated dies with enhanced thermal performance

Encapsulated dies with enhanced thermal performance

Flip chip module with enhanced properties

Connection using conductive vias

Semiconductor package having a substrate structure with selective s...

Flip chip module with enhanced properties

Encapsulated dies with enhanced thermal performance

Laminate variables measured electrically

Flip chip module with enhanced properties

Encapsulated dies with enhanced thermal performance

Encapsulated dies with enhanced thermal performance

Electronic modules having grounded electromagnetic shields

Low pressure encapsulant for size-reduced semiconductor package

Encapsulated dies with enhanced thermal performance

Encapsulated dies with enhanced thermal performance

Patents Applicationslast 30 patents

SEMICONDUCTOR DIE LEVEL STRESS DETECTION IN PACKAGE UTILIZING STRAI...

SYSTEM IN A PACKAGE (SIP) WITH AIR CAVITY AND EPOXY SEAL

COMPARTMENTALIZED SHIELDING OF A MODULE UTILIZING SELF-SHIELDED SUB...

ELECTRONIC DEVICE WITH SOLDER INTERCONNECT AND MULTIPLE MATERIAL EN...

CONTACT PADS FOR ELECTRONIC SUBSTRATES AND RELATED METHODS

SHIELDED ELECTRONIC MODULES AND METHODS OF FORMING THE SAME UTILIZI...

CONTACT PADS FOR ELECTRONIC SUBSTRATES AND RELATED METHODS

SHIELDED ELECTRONIC MODULES AND METHODS OF FORMING THE SAME UTILIZI...

ELECTROMAGNETIC SHIELDS FOR SUB-MODULES

PROCESS FOR MOLDING A BACK SIDE WAFER SINGULATION GUIDE

ELECTROMAGNETIC SHIELDS FOR SUB-MODULES

SEGMENTED SHIELDING USING WIREBONDS

SUBSTRATE STRUCTURE WITH SELECTIVE SURFACE FINISHES FOR FLIP CHIP A...

DOUBLE-SIDED MODULE WITH ELECTROMAGNETIC SHIELDING

USING AN INTERCONNECT BUMP TO TRAVERSE THROUGH A PASSIVATION LAYER...

ELECTROMAGNETIC SHIELDING FOR INTEGRATED CIRCUIT MODULES

LOW PRESSURE ENCAPSULANT FOR SIZE-REDUCED SEMICONDUCTOR PACKAGE

SUBSTRATE STRUCTURE WITH SELECTIVE SURFACE FINISHES FOR FLIP CHIP A...

SEMICONDUCTOR PACKAGE HAVING A SUBSTRATE STRUCTURE WITH SELECTIVE S...

USING AN INTERCONNECT BUMP TO TRAVERSE THROUGH A PASSIVATION LAYER...

FLIP CHIP MODULE WITH ENHANCED PROPERTIES

ENCAPSULATED DIES WITH ENHANCED THERMAL PERFORMANCE

ENCAPSULATED DIES WITH ENHANCED THERMAL PERFORMANCE

CONNECTION USING CONDUCTIVE VIAS

ELECTRONIC MODULES HAVING GROUNDED ELECTROMAGNETIC SHIELDS

CONNECTION USING CONDUCTIVE VIAS

SURFACE FINISH FOR CONDUCTIVE FEATURES ON SUBSTRATES

USING AN INTERCONNECT BUMP TO TRAVERSE THROUGH A PASSIVATION LAYER...

LAMINATE VARIABLES MEASURED ELECTRICALLY

CONNECTION USING CONDUCTIVE VIAS